Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
From: Joakim Tjernlund <hidden>
Date: 2009-10-05 18:52:54
From: Joakim Tjernlund <hidden>
Date: 2009-10-05 18:52:54
Scott Wood [off-list ref] wrote on 05/10/2009 20:24:29:
On Sat, Oct 03, 2009 at 10:05:46AM +0200, Joakim Tjernlund wrote:quoted
Scott Wood [off-list ref] wrote on 02/10/2009 23:49:49:quoted
Adding a tlbil_va to do_page_fault makes the problem go away for me (on top of your "merge" branch) -- none of the other changes in this thread do (assuming I didn't miss any). FWIW, when it gets stuck on a fault, DSISR is 0xc0000000, and handle_mm_fault returns zero.OK, that is a no translation error for a load (assuming trap is 0x400)Yes, 0x400.quoted
Do you know what insn this is?Various lbz and lwz.
OK, this rules out any dcbX problem. Perhaps you can try any of Bens ideas? Not sure what they were but hopefully you and Ben do :) Preferably after you have tested my new patches :) Jocke