Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2009-10-04 20:28:52
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2009-10-04 20:28:52
I have managed to update the TLB code to make proper use of dirty and accessed states. Advantages are: - I/D TLB Miss never needs to write to the linux pte, saving a few cycles
That's good, that leaves us with only 40x to fix now. Also we can remove atomic updates of PTEs for all non-hash. It's pointless on those CPUs anyway.
- Accessed is only set by I/D TLB Error, should be a plus when SWAP is used.
No need for that neither. ISI/DSI shouldn't touch the PTE. They should just fall back to C code which takes care of it all.l
- _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly
and there will be no extra DTLB Error to actually set the changed bit
when a page has been made dirty.
- Proper RO/RW mapping of user space.
Cons:
- 4 more insn in TLB Miss handlers, but the since the linux pte isn't
written it should still be a win.
However, I did this on my 2.4 tree but I can port it to 2.6 if you guys
can test it for me.Why don't you use and test 2.6 ? :-) Cheers, Ben.