Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
From: Joakim Tjernlund <hidden>
Date: 2009-10-04 20:15:15
Scott Wood [off-list ref] wrote on 02/10/2009 23:49:49:
On Thu, Oct 01, 2009 at 08:35:59AM +1000, Benjamin Herrenschmidt wrote:quoted
quoted
From what I can see, the TLB miss code will check _PAGE_PRESENT, andwhen not set, it will -still- insert something into the TLB (unlike all other CPU types that go straight to data access faults from there). So we end up populating with those unpopulated entries that will then cause us to take a DSI (or ISI) instead of a TLB miss the next time around ... and so we need to remove them once we do that, no ? IE. Once we have actually put a valid PTE in. At least that's my understanding and why I believe we should always have tlbil_va() in set_pte() and ptep_set_access_flags(), which boils down in putting it into the 2 "filter" functions in the new code. Well.. actually, the ptep_set_access_flags() will already do a flush_tlb_page_nohash() when the PTE is changed. So I suppose all we really need here would be in set_pte_filter(), to do the same if we are writing a PTE that has _PAGE_PRESENT, at least on 8xx. But just unconditionally doing a tlbil_va() in both the filter functions shouldn't harm and also fix the problem, though Rex seems to indicate that is not the case.Adding a tlbil_va to do_page_fault makes the problem go away for me (on top of your "merge" branch) -- none of the other changes in this thread do (assuming I didn't miss any). FWIW, when it gets stuck on a fault, DSISR is 0xc0000000, and handle_mm_fault returns zero.
Scott and Rex
I have managed to update the TLB code to make proper use of dirty and accessed states.
Advantages are:
- I/D TLB Miss never needs to write to the linux pte, saving a few cycles
- Accessed is only set by I/D TLB Error, should be a plus when SWAP is used.
- _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly
and there will be no extra DTLB Error to actually set the changed bit
when a page has been made dirty.
- Proper RO/RW mapping of user space.
Cons:
- 4 more insn in TLB Miss handlers, but the since the linux pte isn't
written it should still be a win.
However, I did this on my 2.4 tree but I can port it to 2.6 if you guys
can test it for me.
Jocke