Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
From: Joakim Tjernlund <hidden>
Date: 2009-10-03 09:29:14
Benjamin Herrenschmidt [off-list ref] wrote on 03/10/2009 10:31:18:
On Sat, 2009-10-03 at 10:05 +0200, Joakim Tjernlund wrote:quoted
Cannot shake the feeling that it this snip of code that causes it lwz r11, 0(r10) /* Get the level 1 entry */ rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ beq 2f /* If zero, don't try to find a pte */ Perhaps we can do something better? I still feel that we need to force a TLB Error as the TLBMiss does not set DSISR so we have no way of knowing if it is an load or store.Can't we manufacture a DSISR and branch to the right function ?
Not if we want know if it is a load or store. There is no info to manufacture a DSISR from. The best we can do here is try getting the RPN physical page number correct. Perhaps something like this will do: /* Copy 20 msb from MD_EPN to r20 to get the correct page * number. Do not rely on DAR since the dcxx instructions fails * to update DAR when they cause a DTLB Miss */ mfspr r21, MD_EPN li r20, 0x0 rlwimi r20, r21, 0, 0, 19 Then go back and set the RPN accordingly. The 8xx is different as as it will force a TLB error every time it needs to deal with a page fault. I suspect adding if (!ret) _tlbil_va(address); in do_page_fault() will do the trick too. So yes, there is a missing _tlbil_va() missing for 8xx somewhere but there is something more too. Maybe your new filter functions and my powerpc, 8xx: DTLB Error must check for more errors. will do the trick? Jocke