Thread (58 messages) 58 messages, 4 authors, 2009-10-05

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2009-10-03 08:31:31

On Sat, 2009-10-03 at 10:05 +0200, Joakim Tjernlund wrote:
Cannot shake the feeling that it this snip of code that causes it
        lwz     r11, 0(r10)     /* Get the level 1 entry */
        rlwinm. r10, r11,0,0,19 /* Extract page descriptor page
address */
        beq     2f              /* If zero, don't try to find a pte */
Perhaps we can do something better? I still feel that we need to
force a TLB Error as the TLBMiss does not set DSISR so we have no way
of
knowing if it is an load or store.
Can't we manufacture a DSISR and branch to the right function ?

Ben.
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