Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
From: Joakim Tjernlund <hidden>
Date: 2009-09-25 08:43:22
quoted hunk ↗ jump to hunk
quoted
I think there's more finishyness to 8xx than we thought. IE. That tlbil_va might have more reasons to be there than what the comment seems to advertize. Can you try to move it even higher up ? IE. Unconditionally at the beginning of set_pte_filter ? Also, if that doesn't help, can you try putting one in set_access_flags_filter() just below ?Ok, I got a refresher on the whole concept of "unpopulated TLB entries" on 8xx, and that's damn scary. I think what mislead me initially is that the comment around the workaround is simply not properly describing the extent of the problem :-) So I'm not going to make the 8xx TLB miss code sane, that's beyond what I'm prepare to do with it, but I suspect that this should fix it (on top of upstream). Let me know if that's enough or if we also need to put one of these in ptep_set_access_flags(). Please let me know if that works for you. Cheers, Ben.diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c index 5304093..7a8e676 100644 --- a/arch/powerpc/mm/pgtable.c +++ b/arch/powerpc/mm/pgtable.c@@ -170,6 +170,16 @@ struct page * maybe_pte_to_page(pte_t pte) static pte_t set_pte_filter(pte_t pte, unsigned long addr) { +#ifdef CONFIG_8xx + /* 8xx has a weird concept of "unpopulated" entries. When we take + * a TLB miss for a non-valid PTE, we insert such an entry which + * causes a page fault the next time around. This entry must now + * be kicked out or we'll just fault again + */ + /* 8xx doesn't care about PID, size or ind args */ + _tlbil_va(addr, 0, 0, 0); +#endif /* CONFIG_8xx */ +
The main problem with 8xx it does not update the DAR register in the TLB Miss/Fault handlers for cache instructions :( It on old bug that was found only some years ago. I think the old comment is correct though, as I recall it was Marcelo that found the problem and added the workaround. Jocke