Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
From: Joakim Tjernlund <hidden>
Date: 2009-09-29 08:14:01
Subsystem:
linux for powerpc (32-bit and 64-bit), the rest · Maintainers:
Madhavan Srinivasan, Michael Ellerman, Linus Torvalds
Benjamin Herrenschmidt [off-list ref] wrote on 29/09/2009 09:07:37:
On Tue, 2009-09-29 at 08:26 +0200, Joakim Tjernlund wrote:quoted
quoted
I've tried sticking tlbil_va() in those places, nothing seems tohelp.quoted
In some cases userspace is slow, in other cases userspace is fasterandquoted
unstable: sometimes commands hang, sometimes I am able to ctrl-c and and kill it, sometimes I get other strange crashes or falures (sofar noquoted
kernel oopses though).This is exactly what you get when the "cache insn does not update DAR" bug hits you.But then why was it working fine before ? Or it wasn't ?
hmm, yes. You do get this and mysterious SEGV if you hit the but so does other bugs too so this is probably due to missing invalidation. I suspect that something like below will fix the problem and is the "correct" fix(untested, not even compiled):
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 52ff8c5..f579a11 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S@@ -428,7 +428,7 @@ DataStoreTLBMiss: * set. All other Linux PTE bits control the behavior * of the MMU. */ -2: li r11, 0x00f0 + li r11, 0x00f0 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
@@ -441,7 +441,23 @@ DataStoreTLBMiss: lwz r3, 8(r0) #endif rfi +2: + /* Copy 20 msb from MD_EPN to DAR since the dcxx instructions fails + * to update DAR when they cause a DTLB Miss. + */ + mfspr r11, SPRN_MD_EPN + mfspr r10, SPRN_DAR + rlwimi r10, r11, 0, 0, 19 + mtspr SPRN_DAR, r10 + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcr r11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + b DataAccess /* This is an instruction TLB error on the MPC8xx. This could be due * to many reasons, such as executing guarded memory or illegal instruction * addresses. There is nothing to do but handle a big time error fault.