Re: [PATCH 3/3] net: stmmac: Add DWMAC glue layer for Renesas GBETH

Hi Russell,

On Sun, Mar 2, 2025 at 7:33 PM Russell King (Oracle)
[off-list ref] wrote:

quoted

On Sun, Mar 02, 2025 at 06:18:08PM +0000, Prabhakar wrote:

quoted

+     gbeth->dev = dev;
+     gbeth->regs = stmmac_res.addr;
+     plat_dat->bsp_priv = gbeth;
+     plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;

Thanks for using that!

Yep, it shortens the glue driver further.

quoted

quoted

+     plat_dat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY |
+                        STMMAC_FLAG_EN_TX_LPI_CLOCKGATING |

I would like to know what value tx_clk_stop is in
stmmac_mac_enable_tx_lpi() for your setup. Ideally, stmmac should
use the capability report from the PHY to decide whether the
transmit clock can be gated, but sadly we haven't had any support
in phylib/phylink for that until recently, and I haven't modified
stmmac to allow use of that. However, it would be good to gain
knowledge in this area.

tx_clk_stop =1,

root@rzv2h-evk-alpha:~# ifconfig eth0 up
[  587.830436] renesas-gbeth 15c30000.ethernet eth0: Register
MEM_TYPE_PAGE_POOL RxQ-0
[  587.838636] renesas-gbeth 15c30000.ethernet eth0: Register
MEM_TYPE_PAGE_POOL RxQ-1
[  587.846792] renesas-gbeth 15c30000.ethernet eth0: Register
MEM_TYPE_PAGE_POOL RxQ-2
[  587.854734] renesas-gbeth 15c30000.ethernet eth0: Register
MEM_TYPE_PAGE_POOL RxQ-3
[  587.926860] renesas-gbeth 15c30000.ethernet eth0: PHY [stmmac-0:00]
driver [Microchip KSZ9131 Gigabit PHY] (irq=POLL)
[  587.949380] dwmac4: Master AXI performs fixed burst length
[  587.954910] renesas-gbeth 15c30000.ethernet eth0: No Safety
Features support found
[  587.962556] renesas-gbeth 15c30000.ethernet eth0: IEEE 1588-2008
Advanced Timestamp supported
[  587.971420] renesas-gbeth 15c30000.ethernet eth0: registered PTP clock
[  587.978004] renesas-gbeth 15c30000.ethernet eth0: configuring for
phy/rgmii-id link mode
root@rzv2h-evk-alpha:~# [  591.070448] renesas-gbeth 15c30000.ethernet
eth0: tx_clk_stop=1
[  591.076590] renesas-gbeth 15c30000.ethernet eth0: Link is Up -
1Gbps/Full - flow control rx/tx

With the below diff:

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index aec230353ac4..68f1954e6eea 100644

--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

@@ -1100,6 +1100,7 @@ static int stmmac_mac_enable_tx_lpi(struct

phylink_config *config, u32 timer,
        struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
        int ret;

+       netdev_err(priv->dev, "tx_clk_stop=%d\n", tx_clk_stop);
        priv->tx_lpi_timer = timer;
        priv->eee_active = true;

quoted

quoted

+                        STMMAC_FLAG_RX_CLK_RUNS_IN_LPI |