On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:

Il 18/02/22 10:16, Allen-KH Cheng ha scritto:

quoted

Add xhci node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <redacted>
---
  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25
++++++++++++++++++++++++
  1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi

b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 61aadd7bd397..ce18d692175f 100644

--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi

@@ -875,6 +875,31 @@
  			#clock-cells = <1>;
  		};
  
+		u3phy0: usb-phy@11e40000 {
+			compatible = "mediatek,mt8192-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;

This can be better:
			#address-cells = <1>;

			#size-cells = <1>;
			ranges = <0 0 0x11e40000 0x1000>

Hi Angelo,

Thanks for your surgestion, this's good for me,

I will update in next version.

Best regards,
Allen

quoted

+			status = "okay";
+
+			u2port0: usb-phy@11e40000 {

			u2port0: usb-phy@0 {

quoted

+				reg = <0 0x11e40000 0 0x700>;

				reg = <0x0 0x700>;

quoted

+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+
+			u3port0: usb-phy@11e40700 {
+				reg = <0 0x11e40700 0 0x900>;

			u3port0: usb-phy@700 {
				reg = <0x700 0x900>;

quoted

+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				status = "okay";
+			};
+		};
+
  		i2c0: i2c@11f00000 {
  			compatible = "mediatek,mt8192-i2c";
  			reg = <0 0x11f00000 0 0x1000>,

Thanks,
Angelo

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