Add display nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <redacted>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e3314cdc7c1a..026f2d8141b0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi

@@ -32,6 +32,11 @@
                i2c7 = &i2c7;
                i2c8 = &i2c8;
                i2c9 = &i2c9;
+               ovl0 = &ovl0;
+               ovl-2l0 = &ovl_2l0;
+               ovl-2l2 = &ovl_2l2;
+               rdma0 = &rdma0;
+               rdma4 = &rdma4;
        };

        clk26m: oscillator0 {

@@ -1224,6 +1229,13 @@
                        #clock-cells = <1>;
                };

+               mutex: mutex@14001000 {
+                       compatible = "mediatek,mt8192-disp-mutex";
+                       reg = <0 0x14001000 0 0x1000>;
+                       interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+                       clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+               };
+
                smi_common: smi@14002000 {
                        compatible = "mediatek,mt8192-smi-common";
                        reg = <0 0x14002000 0 0x1000>;

@@ -1255,6 +1267,109 @@
                        power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
                };

+               ovl0: ovl@14005000 {
+                       compatible = "mediatek,mt8192-disp-ovl";
+                       reg = <0 0x14005000 0 0x1000>;
+                       interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+                       clocks = <&mmsys CLK_MM_DISP_OVL0>;
+                       iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+                                <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+               };
+
+               ovl_2l0: ovl@14006000 {
+                       compatible = "mediatek,mt8192-disp-ovl-2l";
+                       reg = <0 0x14006000 0 0x1000>;
+                       interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+                       clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+                       iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+                                <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+               };
+
+               rdma0: rdma@14007000 {
+                       compatible = "mediatek,mt8192-disp-rdma";
+                       reg = <0 0x14007000 0 0x1000>;
+                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+                       clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+                       iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+                       mediatek,larb = <&larb0>;
+                       mediatek,rdma-fifo-size = <5120>;
+                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+               };
+
+               color0: color@14009000 {
+                       compatible = "mediatek,mt8192-disp-color",
+                                    "mediatek,mt8173-disp-color";
+                       reg = <0 0x14009000 0 0x1000>;
+                       interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+                       clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+               };
+
+               ccorr0: ccorr@1400a000 {
+                       compatible = "mediatek,mt8192-disp-ccorr";
+                       reg = <0 0x1400a000 0 0x1000>;
+                       interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+                       clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+               };
+
+               aal0: aal@1400b000 {
+                       compatible = "mediatek,mt8192-disp-aal";