[PATCH 2/8] ARM: Implement read/write for ownership in theARMv6 DMA cache ops
From: Russell King - ARM Linux <hidden>
Date: 2010-05-17 10:03:42
From: Russell King - ARM Linux <hidden>
Date: 2010-05-17 10:03:42
On Mon, May 17, 2010 at 12:50:01PM +0300, Ronen Shitrit wrote:
If a speculative prefetch occurs (eg, to prefetch the next ldr) it could evict the dirty cache line that the str just wrote to. Cache replacement algorithms aren't always round-robin. [Ronen Shitrit] only ldr around is the next line, which shouldn't evict the current line, so I don't see any issue.
How can you say that the current line won't be evicted? Do you know the cache replacement algorithm for your CPU that well?