On Mon, 2010-05-17 at 10:51 +0100, Catalin Marinas wrote:

On Sun, 2010-05-16 at 07:29 +0100, Ronen Shitrit wrote:

quoted

Our ARMv6 do speculative rd for both I and D cache...

I'll check with the hardware guys here in ARM and get back to you.

Just for clarification - is your ARMv6 MP processor an ARM11MPCore or
your own MP variant?

In case of Cortex-A9 (ARMv7), the TRM states clearly that it can do
speculative loads into the L1 D-cache and this can be disabled via a bit
in the auxiliary control register. Do you have a similar bit on your
ARMv6 MP processor?

Thanks.

-- 
Catalin