[PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

Subsystems: linux for powerpc (32-bit and 64-bit), the rest

STALE5149d

27 messages, 5 authors, 2012-08-01 · open the first message on its own page

[PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao <hidden>
Date: 2012-07-26 12:54:08

We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function which is architectural better. Also It's convenient for
adding PM support for PCI controller in later patch.

One issue introduced by this architecture is the timing of swiotlb_init.
During PCI initialization the need of swiotlb is determined and this should
be done before swiotlb_init. So a new function to determine swiotlb by
parsing pci ranges is made. This function is called at board_setup_arch
stage which is earlier than swiotlb_init.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one

 arch/powerpc/sysdev/fsl_pci.c |  155 ++++++++++++++++++++++++++++++++---------
 arch/powerpc/sysdev/fsl_pci.h |    9 +--
 2 files changed, 125 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a7b2a60..5228b6b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -823,56 +823,143 @@ static const struct of_device_id pci_ids[] = {
 	{},
 };
 
-struct device_node *fsl_pci_primary;
-
-void __devinit fsl_pci_init(void)
+#ifdef CONFIG_SWIOTLB
+void pci_determine_swiotlb(void)
 {
+	const u32 *ranges;
+	int rlen;
+	int pna;
+	int np;
 	struct device_node *node;
-	struct pci_controller *hose;
-	dma_addr_t max = 0xffffffff;
-
-	/* Callers can specify the primary bus using other means. */
-	if (!fsl_pci_primary) {
-		/* If a PCI host bridge contains an ISA node, it's primary. */
-		node = of_find_node_by_type(NULL, "isa");
-		while ((fsl_pci_primary = of_get_parent(node))) {
-			of_node_put(node);
-			node = fsl_pci_primary;
-
-			if (of_match_node(pci_ids, node))
-				break;
-		}
-	}
+	int memno;
+	u32 pci_space;
+	unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
+	unsigned long long pci_addr_lo = ULLONG_MAX;
+	unsigned long long pci_addr_hi = 0x0;
+	dma_addr_t pci_dma_sz;
 
-	node = NULL;
 	for_each_node_by_type(node, "pci") {
 		if (of_match_node(pci_ids, node)) {
-			/*
-			 * If there's no PCI host bridge with ISA, arbitrarily
-			 * designate one as primary.  This can go away once
-			 * various bugs with primary-less systems are fixed.
-			 */
-			if (!fsl_pci_primary)
-				fsl_pci_primary = node;
-
-			fsl_add_bridge(node, fsl_pci_primary == node);
-			hose = pci_find_hose_for_OF_device(node);
-			max = min(max, hose->dma_window_base_cur +
-					hose->dma_window_size);
+			memno = 0;
+			pna = of_n_addr_cells(node);
+			np = pna + 5;
+			/* Get ranges property */
+			ranges = of_get_property(node, "ranges", &rlen);
+			if (ranges == NULL)
+				return;
+
+			/* Parse outbound MEM window range */
+			while ((rlen -= np * 4) >= 0) {
+				/* Read next ranges element */
+				pci_space = ranges[0];
+				if (!((pci_space >> 24) & 0x2)) {
+					ranges += np;
+					break;
+				}
+				pci_addr = of_read_number(ranges + 1, 2);
+				cpu_addr = of_translate_address(
+						node, ranges + 3);
+				size = of_read_number(ranges + pna + 3, 2);
+				ranges += np;
+
+				/*
+				 * If we failed translation or got a zero-sized
+				 * region (some FW try to feed us with non
+				 * sensical zero sized regions such as power3
+				 * which look like some kind of attempt at
+				 * exposing the VGA memory hole)
+				 */
+				if (cpu_addr == OF_BAD_ADDR || size == 0)
+					continue;
+
+				/*
+				 * Now consume following elements while they
+				 * are contiguous
+				 */
+				for (; rlen >= np * sizeof(u32);
+						ranges += np, rlen -= np * 4) {
+					if (ranges[0] != pci_space)
+						break;
+					pci_next = of_read_number(ranges + 1,
+							2);
+					cpu_next = of_translate_address(node,
+							ranges + 3);
+					if (pci_next != pci_addr + size ||
+						cpu_next != cpu_addr + size)
+						break;
+					size += of_read_number(
+							ranges + pna + 3, 2);
+				}
+
+				/* We support only 3 memory ranges */
+				if (memno >= 3) {
+					printk(KERN_INFO
+							" \\--> Skipped (too many) !\n");
+					continue;
+				}
+
+				pci_addr_lo = min(pci_addr, pci_addr_lo);
+				pci_addr_hi = max(pci_addr + size, pci_addr_hi);
+				memno++;
+			}
 		}
 	}
 
-#ifdef CONFIG_SWIOTLB
+	/* Get PEXCSRBAR size (equal to CCSR size) */
+	node = of_find_node_by_type(NULL, "soc");
+	ranges = of_get_property(node, "ranges", &rlen);
+	if (ranges == NULL)
+		return;
+
+	size = of_read_number(ranges + 3, 1);
+	of_node_put(node);
+
+	if (pci_addr_hi < (0x100000000ull - size))
+		pci_dma_sz = pci_addr_lo;
+	else
+		pci_dma_sz = pci_addr_lo - size;
+
 	/*
 	 * if we couldn't map all of DRAM via the dma windows
 	 * we need SWIOTLB to handle buffers located outside of
 	 * dma capable memory region
 	 */
-	if (memblock_end_of_DRAM() - 1 > max) {
+	if (memblock_end_of_DRAM() > pci_dma_sz) {
 		ppc_swiotlb_enable = 1;
 		set_pci_dma_ops(&swiotlb_dma_ops);
-		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+		ppc_md.pci_dma_dev_setup =
+			pci_dma_dev_setup_swiotlb;
 	}
+}
 #endif
+
+int primary_phb_addr;
+static int __devinit fsl_pci_probe(struct platform_device *pdev)
+{
+	struct pci_controller *hose;
+	bool is_primary;
+
+	if (of_match_node(pci_ids, pdev->dev.of_node)) {
+		struct resource rsrc;
+		of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
+		is_primary = ((rsrc.start & 0xfffff) == primary_phb_addr);
+		fsl_add_bridge(pdev->dev.of_node, is_primary);
+	}
+
+	return 0;
+}
+
+static struct platform_driver fsl_pci_driver = {
+	.driver = {
+		.name = "fsl-pci",
+		.of_match_table = pci_ids,
+	},
+	.probe = fsl_pci_probe,
+};
+
+static int __init fsl_pci_init(void)
+{
+	return platform_driver_register(&fsl_pci_driver);
 }
+arch_initcall(fsl_pci_init);
 #endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index baa0fd1..095392d 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,17 +88,16 @@ struct ccsr_pci {
 	__be32	pex_err_cap_r3;		/* 0x.e34 - PCIE error capture register 0 */
 };
 
+extern int primary_phb_addr;
 extern int fsl_add_bridge(struct device_node *dev, int is_primary);
 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
 extern int mpc83xx_add_bridge(struct device_node *dev);
 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
 
-extern struct device_node *fsl_pci_primary;
-
-#ifdef CONFIG_FSL_PCI
-void fsl_pci_init(void);
+#ifdef CONFIG_SWIOTLB
+extern void pci_determine_swiotlb(void);
 #else
-static inline void fsl_pci_init(void) {}
+static inline void pci_determine_swiotlb(void) {}
 #endif
 
 #endif /* __POWERPC_FSL_PCI_H */
-- 
1.7.5.1

[PATCH V3 2/5] powerpc/fsl-pci: Determine primary bus by looking for ISA node

From: Jia Hongtao <hidden>
Date: 2012-07-26 12:54:12

PCI host bridge is primary bus if it contains an ISA node. But not all boards
fit this rule. Device tree should be updated for all these boards.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Using non-recursive function to find ISA under PCI

 arch/powerpc/include/asm/pci-bridge.h |    1 +
 arch/powerpc/sysdev/fsl_pci.c         |   31 ++++++++++++++++++++++++-------
 arch/powerpc/sysdev/fsl_pci.h         |   12 +++++++++++-
 3 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index ac39e6a..b48fa7f 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -20,6 +20,7 @@ struct device_node;
 struct pci_controller {
 	struct pci_bus *bus;
 	char is_dynamic;
+	int is_primary;
 #ifdef CONFIG_PPC64
 	int node;
 #endif
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 5228b6b..97557c5 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -453,6 +453,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 
 	hose->first_busno = bus_range ? bus_range[0] : 0x0;
 	hose->last_busno = bus_range ? bus_range[1] : 0xff;
+	hose->is_primary = is_primary;
 
 	setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
 		PPC_INDIRECT_TYPE_BIG_ENDIAN);
@@ -933,18 +934,34 @@ void pci_determine_swiotlb(void)
 }
 #endif
 
-int primary_phb_addr;
+/* Checkout if PCI contains ISA node (Only scan the children of PCI) */
+static int of_pci_has_isa(struct device_node *pci_node)
+{
+	struct device_node *np;
+
+	read_lock(&devtree_lock);
+	if (!pci_node)
+		return 0;
+	np = pci_node->allnext;
+	for (; np != pci_node->sibling; np = np->allnext) {
+		if (np->type && (of_node_cmp(np->type, "isa") == 0)
+		    && of_node_get(np)) {
+			of_node_put(pci_node);
+			return 1;
+		}
+	}
+	of_node_put(pci_node);
+	read_unlock(&devtree_lock);
+	return 0;
+}
+
 static int __devinit fsl_pci_probe(struct platform_device *pdev)
 {
-	struct pci_controller *hose;
 	bool is_primary;
+	is_primary = of_pci_has_isa(pdev->dev.of_node);
 
-	if (of_match_node(pci_ids, pdev->dev.of_node)) {
-		struct resource rsrc;
-		of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
-		is_primary = ((rsrc.start & 0xfffff) == primary_phb_addr);
+	if (of_match_node(pci_ids, pdev->dev.of_node))
 		fsl_add_bridge(pdev->dev.of_node, is_primary);
-	}
 
 	return 0;
 }
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 095392d..c884e06 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,7 +88,17 @@ struct ccsr_pci {
 	__be32	pex_err_cap_r3;		/* 0x.e34 - PCIE error capture register 0 */
 };
 
-extern int primary_phb_addr;
+
+#ifdef CONFIG_SUSPEND
+struct fsl_pci_private_data {
+	int inbound_num;
+	struct pci_outbound_window_regs __iomem *pci_pow;
+	struct pci_inbound_window_regs __iomem *pci_piw;
+	void *saved_regs;
+};
+#endif
+
+extern int is_has_isa_node(struct device_node *parent);
 extern int fsl_add_bridge(struct device_node *dev, int is_primary);
 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
 extern int mpc83xx_add_bridge(struct device_node *dev);
-- 
1.7.5.1

[PATCH V3 3/5] powerpc/mpc85xx: convert to unified PCI init

From: Jia Hongtao <hidden>
Date: 2012-07-26 12:54:17

PCI initialization is now done by PCI controller driver. In board_setup_arch
stage we don't need PCI init any more but swiotlb should be determined at this
stage.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
We now just apply this for mpc85xx_ds and qemu

 arch/powerpc/kernel/iommu.c.rej          |   22 -----------------
 arch/powerpc/platforms/85xx/common.c     |    9 +++++++
 arch/powerpc/platforms/85xx/mpc85xx_ds.c |   38 +++++++----------------------
 arch/powerpc/platforms/85xx/qemu_e500.c  |    5 +++-
 4 files changed, 22 insertions(+), 52 deletions(-)
 delete mode 100644 arch/powerpc/kernel/iommu.c.rej
diff --git a/arch/powerpc/kernel/iommu.c.rej b/arch/powerpc/kernel/iommu.c.rej
deleted file mode 100644
index 9d10d34..0000000
--- a/arch/powerpc/kernel/iommu.c.rej
+++ /dev/null
@@ -1,22 +0,0 @@
---- arch/powerpc/kernel/iommu.c	2012-06-08 09:01:02.785709100 +1000
-+++ arch/powerpc/kernel/iommu.c	2012-06-08 09:01:07.489784856 +1000
-@@ -33,7 +33,9 @@
- #include <linux/bitmap.h>
- #include <linux/iommu-helper.h>
- #include <linux/crash_dump.h>
-+#include <linux/fault-inject.h>
- #include <asm/io.h>
-+#include <asm/vio.h>
- #include <asm/prom.h>
- #include <asm/iommu.h>
- #include <asm/pci-bridge.h>
-@@ -171,6 +261,9 @@
- 		return DMA_ERROR_CODE;
- 	}
- 
-+	if (should_fail_iommu(dev))
-+		return DMA_ERROR_CODE;
-+
- 	if (handle && *handle)
- 		start = *handle;
- 	else
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 67dac22..303fedb 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -27,6 +27,15 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
 	{ .compatible = "fsl,mpc8548-guts", },
 	/* Probably unnecessary? */
 	{ .compatible = "gpio-leds", },
+	/* For all PCI controllers */
+	{ .compatible = "fsl,mpc8540-pci", },
+	{ .compatible = "fsl,mpc8548-pcie", },
+	{ .compatible = "fsl,p1022-pcie", },
+	{ .compatible = "fsl,p1010-pcie", },
+	{ .compatible = "fsl,p1023-pcie", },
+	{ .compatible = "fsl,p4080-pcie", },
+	{ .compatible = "fsl,qoriq-pcie-v2.3", },
+	{ .compatible = "fsl,qoriq-pcie-v2.2", },
 	{},
 };
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 6d3265f..4e64414 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -117,40 +117,16 @@ void __init mpc85xx_ds_pic_init(void)
 extern int uli_exclude_device(struct pci_controller *hose,
 				u_char bus, u_char devfn);
 
-static struct device_node *pci_with_uli;
-
 static int mpc85xx_exclude_device(struct pci_controller *hose,
 				   u_char bus, u_char devfn)
 {
-	if (hose->dn == pci_with_uli)
+	if (hose->is_primary)
 		return uli_exclude_device(hose, bus, devfn);
 
 	return PCIBIOS_SUCCESSFUL;
 }
 #endif	/* CONFIG_PCI */
 
-static void __init mpc85xx_ds_pci_init(void)
-{
-#ifdef CONFIG_PCI
-	struct device_node *node;
-
-	fsl_pci_init();
-
-	/* See if we have a ULI under the primary */
-
-	node = of_find_node_by_name(NULL, "uli1575");
-	while ((pci_with_uli = of_get_parent(node))) {
-		of_node_put(node);
-		node = pci_with_uli;
-
-		if (pci_with_uli == fsl_pci_primary) {
-			ppc_md.pci_exclude_device = mpc85xx_exclude_device;
-			break;
-		}
-	}
-#endif
-}
-
 /*
  * Setup the architecture
  */
@@ -159,7 +135,11 @@ static void __init mpc85xx_ds_setup_arch(void)
 	if (ppc_md.progress)
 		ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
 
-	mpc85xx_ds_pci_init();
+#ifdef CONFIG_PCI
+	pci_determine_swiotlb();
+	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
+#endif
+
 	mpc85xx_smp_init();
 
 	printk("MPC85xx DS board from Freescale Semiconductor\n");
@@ -175,9 +155,9 @@ static int __init mpc8544_ds_probe(void)
 	return !!of_flat_dt_is_compatible(root, "MPC8544DS");
 }
 
-machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
-machine_device_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
-machine_device_initcall(p2020_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(p2020_ds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
 machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
index 95a2e53..c490b12 100644
--- a/arch/powerpc/platforms/85xx/qemu_e500.c
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -41,7 +41,10 @@ static void __init qemu_e500_setup_arch(void)
 {
 	ppc_md.progress("qemu_e500_setup_arch()", 0);
 
-	fsl_pci_init();
+#ifdef CONFIG_PCI
+	pci_determine_swiotlb();
+#endif
+
 	mpc85xx_smp_init();
 }
 
-- 
1.7.5.1

[PATCH V3 4/5] powerpc/fsl-pci: Add pci inbound/outbound PM support

From: Jia Hongtao <hidden>
Date: 2012-07-26 12:54:17

Power supply for PCI inbound/outbound window registers is off when system
go to deep-sleep state. We save the values of registers before suspend
and restore to registers after resume.

Signed-off-by: Jiang Yutang <redacted>
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
 arch/powerpc/include/asm/pci-bridge.h |    2 +-
 arch/powerpc/sysdev/fsl_pci.c         |  121 +++++++++++++++++++++++++++++++++
 2 files changed, 122 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index b48fa7f..f0f00a7 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -90,9 +90,9 @@ struct pci_controller {
 
 #ifdef CONFIG_PPC64
 	unsigned long buid;
+#endif	/* CONFIG_PPC64 */
 
 	void *private_data;
-#endif	/* CONFIG_PPC64 */
 };
 
 /* These are used for config access before all the PCI probing
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 97557c5..90e7ab9 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -966,12 +966,133 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_SUSPEND
+
+#define PCI_POW_PIW_OFFSET	0xc00
+#define PCI_POW_PIW_SIZE	0x200
+#define PCI_POW_NUMBER		5
+
+static int fsl_pci_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct pci_controller *hose;
+	struct pci_outbound_window_regs *pci_saved_pow;
+	struct pci_inbound_window_regs *pci_saved_piw, *temp_piw;
+	struct resource pci_rsrc;
+	unsigned int i;
+	struct fsl_pci_private_data *sus_info;
+
+	hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
+	of_address_to_resource(pdev->dev.of_node, 0, &pci_rsrc);
+
+	sus_info = kmalloc(
+			sizeof(struct fsl_pci_private_data), GFP_KERNEL);
+	if (!sus_info)
+		return -ENOMEM;
+
+	hose->private_data = sus_info;
+
+	sus_info->pci_pow = ioremap(pci_rsrc.start + PCI_POW_PIW_OFFSET,
+			PCI_POW_PIW_SIZE);
+	if (!sus_info->pci_pow) {
+		dev_err(&pdev->dev, "pci outbound/inbound windows ioremap error!\n");
+		goto err1;
+	}
+
+	sus_info->pci_piw = (struct pci_inbound_window_regs *)
+		((void *)sus_info->pci_pow + PCI_POW_PIW_SIZE) - 1;
+
+	if (of_device_is_compatible(pdev->dev.of_node, "fsl,qoriq-pcie-v2.2"))
+		sus_info->inbound_num = 4;
+	else
+		sus_info->inbound_num = 3;
+
+	sus_info->saved_regs = kmalloc(
+		sizeof(struct pci_outbound_window_regs) * PCI_POW_NUMBER +
+		sizeof(struct pci_inbound_window_regs) * sus_info->inbound_num,
+		GFP_KERNEL);
+	if (!sus_info->saved_regs)
+		goto err2;
+
+	pci_saved_pow = sus_info->saved_regs;
+	for (i = 0; i < PCI_POW_NUMBER; i++) {
+		pci_saved_pow[i].potar = in_be32(&sus_info->pci_pow[i].potar);
+		pci_saved_pow[i].potear = in_be32(&sus_info->pci_pow[i].potear);
+		pci_saved_pow[i].powbar = in_be32(&sus_info->pci_pow[i].powbar);
+		pci_saved_pow[i].powar = in_be32(&sus_info->pci_pow[i].powar);
+	}
+
+	pci_saved_piw = (struct pci_inbound_window_regs *)
+		(pci_saved_pow + PCI_POW_NUMBER);
+	temp_piw = sus_info->pci_piw;
+	for (i = 0; i < sus_info->inbound_num; i++, temp_piw--) {
+		pci_saved_piw[i].pitar = in_be32(&temp_piw->pitar);
+		pci_saved_piw[i].piwbar = in_be32(&temp_piw->piwbar);
+		pci_saved_piw[i].piwbear = in_be32(&temp_piw->piwbear);
+		pci_saved_piw[i].piwar = in_be32(&temp_piw->piwar);
+	}
+
+	return 0;
+
+err2:
+	iounmap(sus_info->pci_pow);
+
+err1:
+	kfree(sus_info);
+	return -ENOMEM;
+}
+
+static int fsl_pci_resume(struct platform_device *pdev)
+{
+	struct pci_controller *hose;
+	struct pci_outbound_window_regs *pci_saved_pow;
+	struct pci_inbound_window_regs *pci_saved_piw, *temp_piw;
+	unsigned int i;
+	struct fsl_pci_private_data *sus_info;
+
+	hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
+	sus_info = (struct fsl_pci_private_data *)hose->private_data;
+
+	if (!sus_info->pci_pow || !sus_info->pci_piw || !sus_info->saved_regs)
+		return 0;
+
+	pci_saved_pow = sus_info->saved_regs;
+	for (i = 0; i < PCI_POW_NUMBER; i++) {
+		out_be32(&sus_info->pci_pow[i].potar, pci_saved_pow[i].potar);
+		out_be32(&sus_info->pci_pow[i].potear, pci_saved_pow[i].potear);
+		out_be32(&sus_info->pci_pow[i].powbar, pci_saved_pow[i].powbar);
+		out_be32(&sus_info->pci_pow[i].powar, pci_saved_pow[i].powar);
+	}
+
+	pci_saved_piw = (struct pci_inbound_window_regs *)
+		(pci_saved_pow + PCI_POW_NUMBER);
+	temp_piw = sus_info->pci_piw;
+	for (i = 0; i < sus_info->inbound_num; i++, temp_piw--) {
+		out_be32(&temp_piw->pitar, pci_saved_piw[i].pitar);
+		out_be32(&temp_piw->piwbar, pci_saved_piw[i].piwbar);
+		out_be32(&temp_piw->piwbear, pci_saved_piw[i].piwbear);
+		out_be32(&temp_piw->piwar, pci_saved_piw[i].piwar);
+	}
+	iounmap(sus_info->pci_pow);
+	kfree(sus_info->saved_regs);
+	sus_info->saved_regs = NULL;
+	kfree(sus_info);
+	sus_info = NULL;
+	hose->private_data = NULL;
+
+	return 0;
+}
+#endif
+
 static struct platform_driver fsl_pci_driver = {
 	.driver = {
 		.name = "fsl-pci",
 		.of_match_table = pci_ids,
 	},
 	.probe = fsl_pci_probe,
+#ifdef CONFIG_SUSPEND
+	.suspend	= fsl_pci_suspend,
+	.resume		= fsl_pci_resume,
+#endif
 };
 
 static int __init fsl_pci_init(void)
-- 
1.7.5.1

[PATCH V3 5/5] Edac/85xx: Register mpc85xx_pci_err_driver by fsl_pci_driver

From: Jia Hongtao <hidden>
Date: 2012-07-26 12:54:20

From: Chunhe Lan <redacted>

Now we registered pci controllers as platform devices. It will make edac
driver failed to register pci nodes as platform devices too. So we combine
two initialization code as one platform driver.

Signed-off-by: Chunhe Lan <redacted>
Signed-off-by: Li Yang <redacted>
Signed-off-by: Jia Hongtao <redacted>
---
 arch/powerpc/sysdev/fsl_pci.c |    4 +++
 arch/powerpc/sysdev/fsl_pci.h |    4 +++
 drivers/edac/mpc85xx_edac.c   |   43 +++++++++++-----------------------------
 3 files changed, 20 insertions(+), 31 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 90e7ab9..6311d09 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -963,6 +963,10 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev)
 	if (of_match_node(pci_ids, pdev->dev.of_node))
 		fsl_add_bridge(pdev->dev.of_node, is_primary);
 
+#ifdef CONFIG_EDAC_MPC85XX
+	mpc85xx_pci_err_probe(pdev);
+#endif
+
 	return 0;
 }
 
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index c884e06..9845133 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -110,5 +110,9 @@ extern void pci_determine_swiotlb(void);
 static inline void pci_determine_swiotlb(void) {}
 #endif
 
+#ifdef CONFIG_EDAC_MPC85XX
+extern int mpc85xx_pci_err_probe(struct platform_device *op);
+#endif
+
 #endif /* __POWERPC_FSL_PCI_H */
 #endif /* __KERNEL__ */
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index 0e37462..e4b6113 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -200,7 +200,7 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
+int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
 {
 	struct edac_pci_ctl_info *pci;
 	struct mpc85xx_pci_pdata *pdata;
@@ -214,6 +214,16 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
 	if (!pci)
 		return -ENOMEM;
 
+	/* make sure error reporting method is sane */
+	switch (edac_op_state) {
+	case EDAC_OPSTATE_POLL:
+	case EDAC_OPSTATE_INT:
+		break;
+	default:
+		edac_op_state = EDAC_OPSTATE_INT;
+		break;
+	}
+
 	pdata = pci->pvt_info;
 	pdata->name = "mpc85xx_pci_err";
 	pdata->irq = NO_IRQ;
@@ -303,6 +313,7 @@ err:
 	devres_release_group(&op->dev, mpc85xx_pci_err_probe);
 	return res;
 }
+EXPORT_SYMBOL(mpc85xx_pci_err_probe);
 
 static int mpc85xx_pci_err_remove(struct platform_device *op)
 {
@@ -326,27 +337,6 @@ static int mpc85xx_pci_err_remove(struct platform_device *op)
 	return 0;
 }
 
-static struct of_device_id mpc85xx_pci_err_of_match[] = {
-	{
-	 .compatible = "fsl,mpc8540-pcix",
-	 },
-	{
-	 .compatible = "fsl,mpc8540-pci",
-	},
-	{},
-};
-MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
-
-static struct platform_driver mpc85xx_pci_err_driver = {
-	.probe = mpc85xx_pci_err_probe,
-	.remove = __devexit_p(mpc85xx_pci_err_remove),
-	.driver = {
-		.name = "mpc85xx_pci_err",
-		.owner = THIS_MODULE,
-		.of_match_table = mpc85xx_pci_err_of_match,
-	},
-};
-
 #endif				/* CONFIG_PCI */
 
 /**************************** L2 Err device ***************************/
@@ -1193,12 +1183,6 @@ static int __init mpc85xx_mc_init(void)
 	if (res)
 		printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
 
-#ifdef CONFIG_PCI
-	res = platform_driver_register(&mpc85xx_pci_err_driver);
-	if (res)
-		printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
-#endif
-
 #ifdef CONFIG_FSL_SOC_BOOKE
 	pvr = mfspr(SPRN_PVR);
 
@@ -1235,9 +1219,6 @@ static void __exit mpc85xx_mc_exit(void)
 		on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
 	}
 #endif
-#ifdef CONFIG_PCI
-	platform_driver_unregister(&mpc85xx_pci_err_driver);
-#endif
 	platform_driver_unregister(&mpc85xx_l2_err_driver);
 	platform_driver_unregister(&mpc85xx_mc_err_driver);
 }
-- 
1.7.5.1

Re: [PATCH V3 3/5] powerpc/mpc85xx: convert to unified PCI init

From: Kumar Gala <hidden>
Date: 2012-07-26 17:46:46

On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
PCI initialization is now done by PCI controller driver. In =
board_setup_arch
stage we don't need PCI init any more but swiotlb should be determined =
at this
stage.
=20
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
We now just apply this for mpc85xx_ds and qemu
=20
arch/powerpc/kernel/iommu.c.rej          |   22 -----------------
arch/powerpc/platforms/85xx/common.c     |    9 +++++++
arch/powerpc/platforms/85xx/mpc85xx_ds.c |   38 =
+++++++----------------------
arch/powerpc/platforms/85xx/qemu_e500.c  |    5 +++-
4 files changed, 22 insertions(+), 52 deletions(-)
delete mode 100644 arch/powerpc/kernel/iommu.c.rej
removal of iommu.c.rej is handled by:

commit 668fcb6972177489bdc01a66d697c3b494aa8a24
Author: Benjamin Herrenschmidt [off-list ref]
Date:   Mon Jul 23 09:38:53 2012 +1000

    Remove stale .rej file

- k=

Re: [PATCH V3 3/5] powerpc/mpc85xx: convert to unified PCI init

From: Kumar Gala <hidden>
Date: 2012-07-26 17:47:57

On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
PCI initialization is now done by PCI controller driver. In =
board_setup_arch
stage we don't need PCI init any more but swiotlb should be determined =
at this
stage.
=20
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
We now just apply this for mpc85xx_ds and qemu
=20
arch/powerpc/kernel/iommu.c.rej          |   22 -----------------
arch/powerpc/platforms/85xx/common.c     |    9 +++++++
arch/powerpc/platforms/85xx/mpc85xx_ds.c |   38 =
+++++++----------------------
quoted hunk
arch/powerpc/platforms/85xx/qemu_e500.c  |    5 +++-
4 files changed, 22 insertions(+), 52 deletions(-)
delete mode 100644 arch/powerpc/kernel/iommu.c.rej
=20
diff --git a/arch/powerpc/kernel/iommu.c.rej =
b/arch/powerpc/kernel/iommu.c.rej
quoted hunk
deleted file mode 100644
index 9d10d34..0000000
--- a/arch/powerpc/kernel/iommu.c.rej
+++ /dev/null
@@ -1,22 +0,0 @@
---- arch/powerpc/kernel/iommu.c	2012-06-08 09:01:02.785709100 =
+1000
-+++ arch/powerpc/kernel/iommu.c	2012-06-08 09:01:07.489784856 =
+1000
quoted hunk
-@@ -33,7 +33,9 @@
- #include <linux/bitmap.h>
- #include <linux/iommu-helper.h>
- #include <linux/crash_dump.h>
-+#include <linux/fault-inject.h>
- #include <asm/io.h>
-+#include <asm/vio.h>
- #include <asm/prom.h>
- #include <asm/iommu.h>
- #include <asm/pci-bridge.h>
-@@ -171,6 +261,9 @@
- 		return DMA_ERROR_CODE;
- 	}
-=20
-+	if (should_fail_iommu(dev))
-+		return DMA_ERROR_CODE;
-+
- 	if (handle && *handle)
- 		start =3D *handle;
- 	else
diff --git a/arch/powerpc/platforms/85xx/common.c =
b/arch/powerpc/platforms/85xx/common.c
quoted hunk
index 67dac22..303fedb 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -27,6 +27,15 @@ static struct of_device_id __initdata =
mpc85xx_common_ids[] =3D {
	{ .compatible =3D "fsl,mpc8548-guts", },
	/* Probably unnecessary? */
	{ .compatible =3D "gpio-leds", },
+	/* For all PCI controllers */
+	{ .compatible =3D "fsl,mpc8540-pci", },
+	{ .compatible =3D "fsl,mpc8548-pcie", },
+	{ .compatible =3D "fsl,p1022-pcie", },
+	{ .compatible =3D "fsl,p1010-pcie", },
+	{ .compatible =3D "fsl,p1023-pcie", },
+	{ .compatible =3D "fsl,p4080-pcie", },
Add:

	{ .compatible =3D "fsl,qoriq-pcie-v2.4", },
+	{ .compatible =3D "fsl,qoriq-pcie-v2.3", },
+	{ .compatible =3D "fsl,qoriq-pcie-v2.2", },
	{},
};
- k=

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Kumar Gala <hidden>
Date: 2012-07-26 17:53:17

On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
We unified the Freescale pci/pcie initialization by changing the =
fsl_pci
to a platform driver. In previous PCI code architecture the =
initialization
routine is called at board_setup_arch stage. Now the initialization is =
done
in probe function which is architectural better. Also It's convenient =
for
adding PM support for PCI controller in later patch.
=20
One issue introduced by this architecture is the timing of =
swiotlb_init.
During PCI initialization the need of swiotlb is determined and this =
should
be done before swiotlb_init. So a new function to determine swiotlb by
parsing pci ranges is made. This function is called at =
board_setup_arch
stage which is earlier than swiotlb_init.
=20
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one
=20
arch/powerpc/sysdev/fsl_pci.c |  155 =
++++++++++++++++++++++++++++++++---------
quoted hunk
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
=20
diff --git a/arch/powerpc/sysdev/fsl_pci.c =
b/arch/powerpc/sysdev/fsl_pci.c
quoted hunk
index a7b2a60..5228b6b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -823,56 +823,143 @@ static const struct of_device_id pci_ids[] =3D =
{
	{},
};
=20
-struct device_node *fsl_pci_primary;
-
-void __devinit fsl_pci_init(void)
+#ifdef CONFIG_SWIOTLB
+void pci_determine_swiotlb(void)
{
+	const u32 *ranges;
+	int rlen;
+	int pna;
+	int np;
	struct device_node *node;
-	struct pci_controller *hose;
-	dma_addr_t max =3D 0xffffffff;
-
-	/* Callers can specify the primary bus using other means. */
-	if (!fsl_pci_primary) {
-		/* If a PCI host bridge contains an ISA node, it's =
primary. */
-		node =3D of_find_node_by_type(NULL, "isa");
-		while ((fsl_pci_primary =3D of_get_parent(node))) {
-			of_node_put(node);
-			node =3D fsl_pci_primary;
-
-			if (of_match_node(pci_ids, node))
-				break;
-		}
-	}
+	int memno;
+	u32 pci_space;
+	unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
+	unsigned long long pci_addr_lo =3D ULLONG_MAX;
+	unsigned long long pci_addr_hi =3D 0x0;
+	dma_addr_t pci_dma_sz;
=20
-	node =3D NULL;
	for_each_node_by_type(node, "pci") {
		if (of_match_node(pci_ids, node)) {
-			/*
-			 * If there's no PCI host bridge with ISA, =
arbitrarily
-			 * designate one as primary.  This can go away =
once
-			 * various bugs with primary-less systems are =
fixed.
-			 */
-			if (!fsl_pci_primary)
-				fsl_pci_primary =3D node;
-
-			fsl_add_bridge(node, fsl_pci_primary =3D=3D =
node);
-			hose =3D pci_find_hose_for_OF_device(node);
-			max =3D min(max, hose->dma_window_base_cur +
-					hose->dma_window_size);
+			memno =3D 0;
+			pna =3D of_n_addr_cells(node);
+			np =3D pna + 5;
Don't duplicate code from pci_process_bridge_OF_ranges(), refactor the =
code to have a shared function:
+			/* Get ranges property */
+			ranges =3D of_get_property(node, "ranges", =
&rlen);
+			if (ranges =3D=3D NULL)
+				return;
+
+			/* Parse outbound MEM window range */
+			while ((rlen -=3D np * 4) >=3D 0) {
+				/* Read next ranges element */
+				pci_space =3D ranges[0];
+				if (!((pci_space >> 24) & 0x2)) {
+					ranges +=3D np;
+					break;
+				}
+				pci_addr =3D of_read_number(ranges + 1, =
2);
+				cpu_addr =3D of_translate_address(
+						node, ranges + 3);
+				size =3D of_read_number(ranges + pna + =
3, 2);
+				ranges +=3D np;
+
+				/*
+				 * If we failed translation or got a =
zero-sized
+				 * region (some FW try to feed us with =
non
+				 * sensical zero sized regions such as =
power3
+				 * which look like some kind of attempt =
at
+				 * exposing the VGA memory hole)
+				 */
+				if (cpu_addr =3D=3D OF_BAD_ADDR || size =
=3D=3D 0)
+					continue;
+
+				/*
+				 * Now consume following elements while =
they
+				 * are contiguous
+				 */
+				for (; rlen >=3D np * sizeof(u32);
+						ranges +=3D np, rlen -=3D =
np * 4) {
+					if (ranges[0] !=3D pci_space)
+						break;
+					pci_next =3D =
of_read_number(ranges + 1,
+							2);
+					cpu_next =3D =
of_translate_address(node,
+							ranges + 3);
+					if (pci_next !=3D pci_addr + =
size ||
+						cpu_next !=3D cpu_addr + =
size)
+						break;
+					size +=3D of_read_number(
+							ranges + pna + =
3, 2);
+				}
+
+				/* We support only 3 memory ranges */
+				if (memno >=3D 3) {
+					printk(KERN_INFO
+							" \\--> Skipped =
(too many) !\n");
+					continue;
+				}
+
+				pci_addr_lo =3D min(pci_addr, =
pci_addr_lo);
+				pci_addr_hi =3D max(pci_addr + size, =
pci_addr_hi);
+				memno++;
+			}
		}
	}
=20
-#ifdef CONFIG_SWIOTLB
+	/* Get PEXCSRBAR size (equal to CCSR size) */
+	node =3D of_find_node_by_type(NULL, "soc");
+	ranges =3D of_get_property(node, "ranges", &rlen);
+	if (ranges =3D=3D NULL)
+		return;
+
+	size =3D of_read_number(ranges + 3, 1);
+	of_node_put(node);
+
+	if (pci_addr_hi < (0x100000000ull - size))
+		pci_dma_sz =3D pci_addr_lo;
+	else
+		pci_dma_sz =3D pci_addr_lo - size;
+
	/*
	 * if we couldn't map all of DRAM via the dma windows
	 * we need SWIOTLB to handle buffers located outside of
	 * dma capable memory region
	 */
-	if (memblock_end_of_DRAM() - 1 > max) {
+	if (memblock_end_of_DRAM() > pci_dma_sz) {
		ppc_swiotlb_enable =3D 1;
		set_pci_dma_ops(&swiotlb_dma_ops);
-		ppc_md.pci_dma_dev_setup =3D pci_dma_dev_setup_swiotlb;
+		ppc_md.pci_dma_dev_setup =3D
+			pci_dma_dev_setup_swiotlb;
why the line wrap change?
	}
+}
#endif
+
+int primary_phb_addr;
+static int __devinit fsl_pci_probe(struct platform_device *pdev)
+{
+	struct pci_controller *hose;
+	bool is_primary;
+
+	if (of_match_node(pci_ids, pdev->dev.of_node)) {
+		struct resource rsrc;
+		of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
+		is_primary =3D ((rsrc.start & 0xfffff) =3D=3D =
primary_phb_addr);
+		fsl_add_bridge(pdev->dev.of_node, is_primary);
+	}
+
+	return 0;
+}
+
+static struct platform_driver fsl_pci_driver =3D {
+	.driver =3D {
+		.name =3D "fsl-pci",
+		.of_match_table =3D pci_ids,
+	},
+	.probe =3D fsl_pci_probe,
+};
+
+static int __init fsl_pci_init(void)
+{
+	return platform_driver_register(&fsl_pci_driver);
}
+arch_initcall(fsl_pci_init);
#endif

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Kumar Gala <hidden>
Date: 2012-07-26 18:14:40

On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
We unified the Freescale pci/pcie initialization by changing the =
fsl_pci
to a platform driver. In previous PCI code architecture the =
initialization
routine is called at board_setup_arch stage. Now the initialization is =
done
in probe function which is architectural better. Also It's convenient =
for
adding PM support for PCI controller in later patch.
=20
One issue introduced by this architecture is the timing of =
swiotlb_init.
During PCI initialization the need of swiotlb is determined and this =
should
be done before swiotlb_init. So a new function to determine swiotlb by
parsing pci ranges is made. This function is called at =
board_setup_arch
stage which is earlier than swiotlb_init.
=20
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one
=20
arch/powerpc/sysdev/fsl_pci.c |  155 =
++++++++++++++++++++++++++++++++---------
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
I'd like the SWIOTLB refactoring as a separate patch.  Additionally, the =
order of patches should be as follows:

1. refactor PCI node parsing code
2. add pci_determine_swiotlb (should rename to =
fsl_pci_determine_swiotlb)
3. Determine primary bus by looking for ISA node
4. convert all boards over to fsl_pci_init
5. convert fsl pci to platform driver (edac and other fixes should be =
merged in here)
6. PM support

- k=

Re: [PATCH V3 2/5] powerpc/fsl-pci: Determine primary bus by looking for ISA node

From: Kumar Gala <hidden>
Date: 2012-07-26 18:21:51

On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
PCI host bridge is primary bus if it contains an ISA node. But not all =
boards
fit this rule. Device tree should be updated for all these boards.
I don't really seen any reason for this patch.  We can just use the code =
as Scott wrote it that sets fsl_pci_primary based on search for the isa =
node.
=20
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Using non-recursive function to find ISA under PCI
=20
arch/powerpc/include/asm/pci-bridge.h |    1 +
arch/powerpc/sysdev/fsl_pci.c         |   31 =
++++++++++++++++++++++++-------
quoted hunk
arch/powerpc/sysdev/fsl_pci.h         |   12 +++++++++++-
3 files changed, 36 insertions(+), 8 deletions(-)
=20
diff --git a/arch/powerpc/include/asm/pci-bridge.h =
b/arch/powerpc/include/asm/pci-bridge.h
quoted hunk
index ac39e6a..b48fa7f 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -20,6 +20,7 @@ struct device_node;
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
+	int is_primary;
#ifdef CONFIG_PPC64
	int node;
#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.c =
b/arch/powerpc/sysdev/fsl_pci.c
quoted hunk
index 5228b6b..97557c5 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -453,6 +453,7 @@ int __init fsl_add_bridge(struct device_node *dev, =
int is_primary)
quoted hunk
=20
	hose->first_busno =3D bus_range ? bus_range[0] : 0x0;
	hose->last_busno =3D bus_range ? bus_range[1] : 0xff;
+	hose->is_primary =3D is_primary;
=20
	setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
		PPC_INDIRECT_TYPE_BIG_ENDIAN);
@@ -933,18 +934,34 @@ void pci_determine_swiotlb(void)
}
#endif
=20
-int primary_phb_addr;
+/* Checkout if PCI contains ISA node (Only scan the children of PCI) =
*/
+static int of_pci_has_isa(struct device_node *pci_node)
+{
+	struct device_node *np;
+
+	read_lock(&devtree_lock);
+	if (!pci_node)
+		return 0;
+	np =3D pci_node->allnext;
+	for (; np !=3D pci_node->sibling; np =3D np->allnext) {
+		if (np->type && (of_node_cmp(np->type, "isa") =3D=3D 0)
+		    && of_node_get(np)) {
+			of_node_put(pci_node);
+			return 1;
+		}
+	}
+	of_node_put(pci_node);
+	read_unlock(&devtree_lock);
+	return 0;
+}
+
static int __devinit fsl_pci_probe(struct platform_device *pdev)
{
-	struct pci_controller *hose;
	bool is_primary;
+	is_primary =3D of_pci_has_isa(pdev->dev.of_node);
=20
-	if (of_match_node(pci_ids, pdev->dev.of_node)) {
-		struct resource rsrc;
-		of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
-		is_primary =3D ((rsrc.start & 0xfffff) =3D=3D =
primary_phb_addr);
quoted hunk
+	if (of_match_node(pci_ids, pdev->dev.of_node))
		fsl_add_bridge(pdev->dev.of_node, is_primary);
-	}
=20
	return 0;
}
diff --git a/arch/powerpc/sysdev/fsl_pci.h =
b/arch/powerpc/sysdev/fsl_pci.h
quoted hunk
index 095392d..c884e06 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,7 +88,17 @@ struct ccsr_pci {
	__be32	pex_err_cap_r3;		/* 0x.e34 - PCIE error capture =
register 0 */
};
=20
-extern int primary_phb_addr;
+
+#ifdef CONFIG_SUSPEND
+struct fsl_pci_private_data {
+	int inbound_num;
+	struct pci_outbound_window_regs __iomem *pci_pow;
+	struct pci_inbound_window_regs __iomem *pci_piw;
+	void *saved_regs;
+};
+#endif
+
This struct has nothing to do with this patch
+extern int is_has_isa_node(struct device_node *parent);
Where is is_has_isa_node() defined or used?
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
--=20
1.7.5.1
=20

RE: [PATCH V3 2/5] powerpc/fsl-pci: Determine primary bus by looking for ISA node

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-27 02:16:27

Thanks for all your comments.
Sorry for the mistakes in this patchset.
I am just so eager to push them to upstream.
I will work on the comments very carfully.

Thanks.
-Hongtao.
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:22 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 2/5] powerpc/fsl-pci: Determine primary bus by
looking for ISA node
=20
=20
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
=20
quoted
PCI host bridge is primary bus if it contains an ISA node. But not all
boards
quoted
fit this rule. Device tree should be updated for all these boards.
=20
I don't really seen any reason for this patch.  We can just use the code
as Scott wrote it that sets fsl_pci_primary based on search for the isa
node.
=20
quoted
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Using non-recursive function to find ISA under PCI

arch/powerpc/include/asm/pci-bridge.h |    1 +
arch/powerpc/sysdev/fsl_pci.c         |   31 ++++++++++++++++++++++++--
-----
quoted
arch/powerpc/sysdev/fsl_pci.h         |   12 +++++++++++-
3 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
quoted
index ac39e6a..b48fa7f 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -20,6 +20,7 @@ struct device_node;
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
+	int is_primary;
#ifdef CONFIG_PPC64
	int node;
#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.c
b/arch/powerpc/sysdev/fsl_pci.c
quoted
index 5228b6b..97557c5 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -453,6 +453,7 @@ int __init fsl_add_bridge(struct device_node *dev,
int is_primary)
quoted
	hose->first_busno =3D bus_range ? bus_range[0] : 0x0;
	hose->last_busno =3D bus_range ? bus_range[1] : 0xff;
+	hose->is_primary =3D is_primary;

	setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
		PPC_INDIRECT_TYPE_BIG_ENDIAN);
@@ -933,18 +934,34 @@ void pci_determine_swiotlb(void)
}
#endif

-int primary_phb_addr;
+/* Checkout if PCI contains ISA node (Only scan the children of PCI)
*/
quoted
+static int of_pci_has_isa(struct device_node *pci_node)
+{
+	struct device_node *np;
+
+	read_lock(&devtree_lock);
+	if (!pci_node)
+		return 0;
+	np =3D pci_node->allnext;
+	for (; np !=3D pci_node->sibling; np =3D np->allnext) {
+		if (np->type && (of_node_cmp(np->type, "isa") =3D=3D 0)
+		    && of_node_get(np)) {
+			of_node_put(pci_node);
+			return 1;
+		}
+	}
+	of_node_put(pci_node);
+	read_unlock(&devtree_lock);
+	return 0;
+}
+
static int __devinit fsl_pci_probe(struct platform_device *pdev)
{
-	struct pci_controller *hose;
	bool is_primary;
+	is_primary =3D of_pci_has_isa(pdev->dev.of_node);

-	if (of_match_node(pci_ids, pdev->dev.of_node)) {
-		struct resource rsrc;
-		of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
-		is_primary =3D ((rsrc.start & 0xfffff) =3D=3D primary_phb_addr);
+	if (of_match_node(pci_ids, pdev->dev.of_node))
		fsl_add_bridge(pdev->dev.of_node, is_primary);
-	}

	return 0;
}
diff --git a/arch/powerpc/sysdev/fsl_pci.h
b/arch/powerpc/sysdev/fsl_pci.h
quoted
index 095392d..c884e06 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,7 +88,17 @@ struct ccsr_pci {
	__be32	pex_err_cap_r3;		/* 0x.e34 - PCIE error capture
register 0 */
quoted
};

-extern int primary_phb_addr;
+
+#ifdef CONFIG_SUSPEND
+struct fsl_pci_private_data {
+	int inbound_num;
+	struct pci_outbound_window_regs __iomem *pci_pow;
+	struct pci_inbound_window_regs __iomem *pci_piw;
+	void *saved_regs;
+};
+#endif
+
=20
This struct has nothing to do with this patch
=20
quoted
+extern int is_has_isa_node(struct device_node *parent);
=20
Where is is_has_isa_node() defined or used?
=20
quoted
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
--
1.7.5.1
=20

RE: [PATCH V3 2/5] powerpc/fsl-pci: Determine primary bus by looking for ISA node

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-27 02:57:10

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:22 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 2/5] powerpc/fsl-pci: Determine primary bus by
looking for ISA node
=20
=20
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
=20
quoted
PCI host bridge is primary bus if it contains an ISA node. But not all
boards
quoted
fit this rule. Device tree should be updated for all these boards.
=20
I don't really seen any reason for this patch.  We can just use the code
as Scott wrote it that sets fsl_pci_primary based on search for the isa
node.
=20

I change the way of searching ISA node just because the platform driver
mechanism. Probe function of this driver will be called for each PCI
controller which means more than once. I think the Scott's way is not
perfectly match this situation. Anyway I will find a better way to solve
this by refactoring the Scott's method or using my own way.

Thanks.
-Hongtao.

RE: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-27 08:35:52

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:15 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
=20
quoted
We unified the Freescale pci/pcie initialization by changing the
fsl_pci
quoted
to a platform driver. In previous PCI code architecture the
initialization
quoted
routine is called at board_setup_arch stage. Now the initialization is
done
quoted
in probe function which is architectural better. Also It's convenient
for
quoted
adding PM support for PCI controller in later patch.

One issue introduced by this architecture is the timing of swiotlb_init=
.
quoted
During PCI initialization the need of swiotlb is determined and this
should
quoted
be done before swiotlb_init. So a new function to determine swiotlb by
parsing pci ranges is made. This function is called at board_setup_arch
stage which is earlier than swiotlb_init.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one

arch/powerpc/sysdev/fsl_pci.c |  155 ++++++++++++++++++++++++++++++++--
-------
quoted
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
=20
I'd like the SWIOTLB refactoring as a separate patch.  Additionally, the
order of patches should be as follows:
=20
1. refactor PCI node parsing code
2. add pci_determine_swiotlb (should rename to fsl_pci_determine_swiotlb)
3. Determine primary bus by looking for ISA node
4. convert all boards over to fsl_pci_init
5. convert fsl pci to platform driver (edac and other fixes should be
merged in here)
6. PM support
=20
- k
Should I convert all boards over to fsl_pci_init first and then convert the=
m
over to platform driver again or just convert them direct to platform drive=
r?

Thanks.
-Hongtao.

RE: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-27 10:10:18

Hi kumar,

I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.

Here is the situation:

First, pci_process_bridge_OF_ranges() is a common code using by
so many pci client.

Second, the contents of pci_process_bridge_OF_ranges() twisted
together. It's hard to decouple the function I need for determining
swiotlb with other contents. I tried and found a way to do this
but the shared function need so many parameters which is also
unacceptable.=20

Third, my function to determine swiotlb should know the start
and the end of pci mem space address for all the controllers.
Note that the end of address is for determining where to map
PEXCSRBAR.

If you have any idea for this please let me know.

Thanks.
-Hongtao.

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 1:53 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
=20
quoted
We unified the Freescale pci/pcie initialization by changing the
fsl_pci
quoted
to a platform driver. In previous PCI code architecture the
initialization
quoted
routine is called at board_setup_arch stage. Now the initialization is
done
quoted
in probe function which is architectural better. Also It's convenient
for
quoted
adding PM support for PCI controller in later patch.

One issue introduced by this architecture is the timing of swiotlb_init=
.
quoted
During PCI initialization the need of swiotlb is determined and this
should
quoted
be done before swiotlb_init. So a new function to determine swiotlb by
parsing pci ranges is made. This function is called at board_setup_arch
stage which is earlier than swiotlb_init.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one

arch/powerpc/sysdev/fsl_pci.c |  155 ++++++++++++++++++++++++++++++++--
-------
quoted
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c
b/arch/powerpc/sysdev/fsl_pci.c
quoted
index a7b2a60..5228b6b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -823,56 +823,143 @@ static const struct of_device_id pci_ids[] =3D {
	{},
};

-struct device_node *fsl_pci_primary;
-
-void __devinit fsl_pci_init(void)
+#ifdef CONFIG_SWIOTLB
+void pci_determine_swiotlb(void)
{
+	const u32 *ranges;
+	int rlen;
+	int pna;
+	int np;
	struct device_node *node;
-	struct pci_controller *hose;
-	dma_addr_t max =3D 0xffffffff;
-
-	/* Callers can specify the primary bus using other means. */
-	if (!fsl_pci_primary) {
-		/* If a PCI host bridge contains an ISA node, it's primary.
*/
quoted
-		node =3D of_find_node_by_type(NULL, "isa");
-		while ((fsl_pci_primary =3D of_get_parent(node))) {
-			of_node_put(node);
-			node =3D fsl_pci_primary;
-
-			if (of_match_node(pci_ids, node))
-				break;
-		}
-	}
+	int memno;
+	u32 pci_space;
+	unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
+	unsigned long long pci_addr_lo =3D ULLONG_MAX;
+	unsigned long long pci_addr_hi =3D 0x0;
+	dma_addr_t pci_dma_sz;

-	node =3D NULL;
	for_each_node_by_type(node, "pci") {
		if (of_match_node(pci_ids, node)) {
-			/*
-			 * If there's no PCI host bridge with ISA, arbitrarily
-			 * designate one as primary.  This can go away once
-			 * various bugs with primary-less systems are fixed.
-			 */
-			if (!fsl_pci_primary)
-				fsl_pci_primary =3D node;
-
-			fsl_add_bridge(node, fsl_pci_primary =3D=3D node);
-			hose =3D pci_find_hose_for_OF_device(node);
-			max =3D min(max, hose->dma_window_base_cur +
-					hose->dma_window_size);
+			memno =3D 0;
+			pna =3D of_n_addr_cells(node);
+			np =3D pna + 5;
=20
Don't duplicate code from pci_process_bridge_OF_ranges(), refactor the
code to have a shared function:
=20
quoted
+			/* Get ranges property */
+			ranges =3D of_get_property(node, "ranges", &rlen);
+			if (ranges =3D=3D NULL)
+				return;
+
+			/* Parse outbound MEM window range */
+			while ((rlen -=3D np * 4) >=3D 0) {
+				/* Read next ranges element */
+				pci_space =3D ranges[0];
+				if (!((pci_space >> 24) & 0x2)) {
+					ranges +=3D np;
+					break;
+				}
+				pci_addr =3D of_read_number(ranges + 1, 2);
+				cpu_addr =3D of_translate_address(
+						node, ranges + 3);
+				size =3D of_read_number(ranges + pna + 3, 2);
+				ranges +=3D np;
+
+				/*
+				 * If we failed translation or got a zero-sized
+				 * region (some FW try to feed us with non
+				 * sensical zero sized regions such as power3
+				 * which look like some kind of attempt at
+				 * exposing the VGA memory hole)
+				 */
+				if (cpu_addr =3D=3D OF_BAD_ADDR || size =3D=3D 0)
+					continue;
+
+				/*
+				 * Now consume following elements while they
+				 * are contiguous
+				 */
+				for (; rlen >=3D np * sizeof(u32);
+						ranges +=3D np, rlen -=3D np * 4) {
+					if (ranges[0] !=3D pci_space)
+						break;
+					pci_next =3D of_read_number(ranges + 1,
+							2);
+					cpu_next =3D of_translate_address(node,
+							ranges + 3);
+					if (pci_next !=3D pci_addr + size ||
+						cpu_next !=3D cpu_addr + size)
+						break;
+					size +=3D of_read_number(
+							ranges + pna + 3, 2);
+				}
+
+				/* We support only 3 memory ranges */
+				if (memno >=3D 3) {
+					printk(KERN_INFO
+							" \\--> Skipped (too
many) !\n");
quoted
+					continue;
+				}
+
+				pci_addr_lo =3D min(pci_addr, pci_addr_lo);
+				pci_addr_hi =3D max(pci_addr + size, pci_addr_hi);
+				memno++;
+			}
		}
	}

-#ifdef CONFIG_SWIOTLB
+	/* Get PEXCSRBAR size (equal to CCSR size) */
+	node =3D of_find_node_by_type(NULL, "soc");
+	ranges =3D of_get_property(node, "ranges", &rlen);
+	if (ranges =3D=3D NULL)
+		return;
+
+	size =3D of_read_number(ranges + 3, 1);
+	of_node_put(node);
+
+	if (pci_addr_hi < (0x100000000ull - size))
+		pci_dma_sz =3D pci_addr_lo;
+	else
+		pci_dma_sz =3D pci_addr_lo - size;
+
	/*
	 * if we couldn't map all of DRAM via the dma windows
	 * we need SWIOTLB to handle buffers located outside of
	 * dma capable memory region
	 */
-	if (memblock_end_of_DRAM() - 1 > max) {
+	if (memblock_end_of_DRAM() > pci_dma_sz) {
		ppc_swiotlb_enable =3D 1;
		set_pci_dma_ops(&swiotlb_dma_ops);
-		ppc_md.pci_dma_dev_setup =3D pci_dma_dev_setup_swiotlb;
+		ppc_md.pci_dma_dev_setup =3D
+			pci_dma_dev_setup_swiotlb;
=20
why the line wrap change?
=20
quoted
	}
+}
#endif
+
+int primary_phb_addr;
+static int __devinit fsl_pci_probe(struct platform_device *pdev)
+{
+	struct pci_controller *hose;
+	bool is_primary;
+
+	if (of_match_node(pci_ids, pdev->dev.of_node)) {
+		struct resource rsrc;
+		of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
+		is_primary =3D ((rsrc.start & 0xfffff) =3D=3D primary_phb_addr);
+		fsl_add_bridge(pdev->dev.of_node, is_primary);
+	}
+
+	return 0;
+}
+
+static struct platform_driver fsl_pci_driver =3D {
+	.driver =3D {
+		.name =3D "fsl-pci",
+		.of_match_table =3D pci_ids,
+	},
+	.probe =3D fsl_pci_probe,
+};
+
+static int __init fsl_pci_init(void)
+{
+	return platform_driver_register(&fsl_pci_driver);
}
+arch_initcall(fsl_pci_init);
#endif
=20
=20

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Kumar Gala <hidden>
Date: 2012-07-27 12:47:55

On Jul 27, 2012, at 3:35 AM, Jia Hongtao-B38951 wrote:
=20
=20
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:15 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
=20
quoted
We unified the Freescale pci/pcie initialization by changing the
fsl_pci
quoted
to a platform driver. In previous PCI code architecture the
initialization
quoted
routine is called at board_setup_arch stage. Now the initialization =
is
quoted
done
quoted
in probe function which is architectural better. Also It's =
convenient
quoted
for
quoted
adding PM support for PCI controller in later patch.
=20
One issue introduced by this architecture is the timing of =
swiotlb_init.
quoted
quoted
During PCI initialization the need of swiotlb is determined and this
should
quoted
be done before swiotlb_init. So a new function to determine swiotlb =
by
quoted
quoted
parsing pci ranges is made. This function is called at =
board_setup_arch
quoted
quoted
stage which is earlier than swiotlb_init.
=20
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one
=20
arch/powerpc/sysdev/fsl_pci.c |  155 =
++++++++++++++++++++++++++++++++--
quoted
-------
quoted
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
=20
I'd like the SWIOTLB refactoring as a separate patch.  Additionally, =
the
quoted
order of patches should be as follows:
=20
1. refactor PCI node parsing code
2. add pci_determine_swiotlb (should rename to =
fsl_pci_determine_swiotlb)
quoted
3. Determine primary bus by looking for ISA node
4. convert all boards over to fsl_pci_init
5. convert fsl pci to platform driver (edac and other fixes should be
merged in here)
6. PM support
=20
- k
=20
Should I convert all boards over to fsl_pci_init first and then =
convert them
over to platform driver again or just convert them direct to platform =
driver?

Yes do the fsl_pci_init conversion first.  The reason is we should NOT =
break functionality from one patch to another.

- k=

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Scott Wood <hidden>
Date: 2012-07-27 20:24:41

On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
Hi kumar,

I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done before probe.

Another possibility is to try to handle swiotlb init later -- possibly
by reserving memory for it if the platform indicates it's a possibility
that it will be needed, then freeing the memory if it's not needed.

-Scott

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Kumar Gala <hidden>
Date: 2012-07-27 21:17:30

On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
quoted
Hi kumar,
=20
I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
=20
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done before =
probe.
=20
Another possibility is to try to handle swiotlb init later -- possibly
by reserving memory for it if the platform indicates it's a =
possibility
that it will be needed, then freeing the memory if it's not needed.
=20
-Scott
I think the first option seems reasonable.  Can we leave fsl_pci_init() =
as we now have it and just have the platform driver deal with PM restore =
via calling setup_pci_atmu() [probably need to update setup_pci_atmu to =
handle restore case, but seems like minor changes]

- k

RE: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-30 08:07:40

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 8:47 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 27, 2012, at 3:35 AM, Jia Hongtao-B38951 wrote:
=20
quoted
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:15 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code


On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
quoted
We unified the Freescale pci/pcie initialization by changing the
fsl_pci
quoted
to a platform driver. In previous PCI code architecture the
initialization
quoted
routine is called at board_setup_arch stage. Now the initialization
is
quoted
quoted
done
quoted
in probe function which is architectural better. Also It's convenient
for
quoted
adding PM support for PCI controller in later patch.

One issue introduced by this architecture is the timing of
swiotlb_init.
quoted
quoted
quoted
During PCI initialization the need of swiotlb is determined and this
should
quoted
be done before swiotlb_init. So a new function to determine swiotlb
by
quoted
quoted
quoted
parsing pci ranges is made. This function is called at
board_setup_arch
quoted
quoted
quoted
stage which is earlier than swiotlb_init.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one

arch/powerpc/sysdev/fsl_pci.c |  155
++++++++++++++++++++++++++++++++--
quoted
quoted
-------
quoted
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
I'd like the SWIOTLB refactoring as a separate patch.  Additionally,
the
quoted
quoted
order of patches should be as follows:

1. refactor PCI node parsing code
2. add pci_determine_swiotlb (should rename to
fsl_pci_determine_swiotlb)
quoted
quoted
3. Determine primary bus by looking for ISA node
4. convert all boards over to fsl_pci_init
5. convert fsl pci to platform driver (edac and other fixes should be
merged in here)
6. PM support

- k
Should I convert all boards over to fsl_pci_init first and then convert
them
quoted
over to platform driver again or just convert them direct to platform
driver?
=20
Yes do the fsl_pci_init conversion first.  The reason is we should NOT
break functionality from one patch to another.
=20
- k

Actually, the functionality is not broken, other boards just use the old
Way to init pci controller and it still works.

-Hongtao.

RE: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-30 08:26:51

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Saturday, July 28, 2012 5:17 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
=20
quoted
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
quoted
Hi kumar,

I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done before
probe.
quoted
Another possibility is to try to handle swiotlb init later -- possibly
by reserving memory for it if the platform indicates it's a possibility
that it will be needed, then freeing the memory if it's not needed.

-Scott
=20
I think the first option seems reasonable.  Can we leave fsl_pci_init()
as we now have it and just have the platform driver deal with PM restore
via calling setup_pci_atmu() [probably need to update setup_pci_atmu to
handle restore case, but seems like minor changes]
=20
- k
=20

I think the second option is better if it's hard to decouple swiotlb
determination from pci init. I believe the better architecture that
PCI init in probe function of platform driver will bring us considerable
advantage. I really like to keep the completion of pci controller
platform driver not only for PM support but also for pci init.

-Hongtao.=20

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Kumar Gala <hidden>
Date: 2012-07-30 14:46:54

On Jul 30, 2012, at 3:07 AM, Jia Hongtao-B38951 wrote:
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 8:47 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 27, 2012, at 3:35 AM, Jia Hongtao-B38951 wrote:
=20
quoted
=20
=20
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:15 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li =
Yang-R58472
quoted
quoted
quoted
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
=20
quoted
We unified the Freescale pci/pcie initialization by changing the
fsl_pci
quoted
to a platform driver. In previous PCI code architecture the
initialization
quoted
routine is called at board_setup_arch stage. Now the =
initialization
quoted
is
quoted
quoted
done
quoted
in probe function which is architectural better. Also It's =
convenient
quoted
quoted
quoted
for
quoted
adding PM support for PCI controller in later patch.
=20
One issue introduced by this architecture is the timing of
swiotlb_init.
quoted
quoted
quoted
During PCI initialization the need of swiotlb is determined and =
this
quoted
quoted
quoted
should
quoted
be done before swiotlb_init. So a new function to determine =
swiotlb
quoted
by
quoted
quoted
quoted
parsing pci ranges is made. This function is called at
board_setup_arch
quoted
quoted
quoted
stage which is earlier than swiotlb_init.
=20
Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one
=20
arch/powerpc/sysdev/fsl_pci.c |  155
++++++++++++++++++++++++++++++++--
quoted
quoted
-------
quoted
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
=20
I'd like the SWIOTLB refactoring as a separate patch.  =
Additionally,
quoted
the
quoted
quoted
order of patches should be as follows:
=20
1. refactor PCI node parsing code
2. add pci_determine_swiotlb (should rename to
fsl_pci_determine_swiotlb)
quoted
quoted
3. Determine primary bus by looking for ISA node
4. convert all boards over to fsl_pci_init
5. convert fsl pci to platform driver (edac and other fixes should =
be
quoted
quoted
quoted
merged in here)
6. PM support
=20
- k
=20
Should I convert all boards over to fsl_pci_init first and then =
convert
quoted
them
quoted
over to platform driver again or just convert them direct to =
platform
quoted
driver?
=20
Yes do the fsl_pci_init conversion first.  The reason is we should =
NOT
quoted
break functionality from one patch to another.
=20
- k
=20
=20
Actually, the functionality is not broken, other boards just use the =
old
Way to init pci controller and it still works.
How do you figure?  The platform driver is going to get called on boards =
not yet converted.  So than you will get 2 different inits of PCI going =
on.

- k=

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Kumar Gala <hidden>
Date: 2012-07-30 14:49:12

On Jul 30, 2012, at 3:26 AM, Jia Hongtao-B38951 wrote:
=20
=20
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Saturday, July 28, 2012 5:17 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood =
Scott-B07421;
quoted
Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
=20
quoted
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
quoted
Hi kumar,
=20
I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
=20
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done before
probe.
quoted
=20
Another possibility is to try to handle swiotlb init later -- =
possibly
quoted
quoted
by reserving memory for it if the platform indicates it's a =
possibility
quoted
quoted
that it will be needed, then freeing the memory if it's not needed.
=20
-Scott
=20
I think the first option seems reasonable.  Can we leave =
fsl_pci_init()
quoted
as we now have it and just have the platform driver deal with PM =
restore
quoted
via calling setup_pci_atmu() [probably need to update setup_pci_atmu =
to
quoted
handle restore case, but seems like minor changes]
=20
- k
=20
=20
=20
I think the second option is better if it's hard to decouple swiotlb
determination from pci init. I believe the better architecture that
PCI init in probe function of platform driver will bring us =
considerable
advantage. I really like to keep the completion of pci controller
platform driver not only for PM support but also for pci init.
=20
-Hongtao.=20
=20
Shifting of swiotlb init has a lot more issues.  Why do we need to do =
the PCI init in probe?

- k=

RE: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-31 02:22:23

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Monday, July 30, 2012 10:47 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 30, 2012, at 3:07 AM, Jia Hongtao-B38951 wrote:
=20
quoted
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 8:47 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code


On Jul 27, 2012, at 3:35 AM, Jia Hongtao-B38951 wrote:
quoted
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Friday, July 27, 2012 2:15 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code


On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
quoted
We unified the Freescale pci/pcie initialization by changing the
fsl_pci
quoted
to a platform driver. In previous PCI code architecture the
initialization
quoted
routine is called at board_setup_arch stage. Now the initialization
is
quoted
quoted
done
quoted
in probe function which is architectural better. Also It's
convenient
quoted
quoted
quoted
quoted
for
quoted
adding PM support for PCI controller in later patch.

One issue introduced by this architecture is the timing of
swiotlb_init.
quoted
quoted
quoted
During PCI initialization the need of swiotlb is determined and
this
quoted
quoted
quoted
quoted
should
quoted
be done before swiotlb_init. So a new function to determine swiotlb
by
quoted
quoted
quoted
parsing pci ranges is made. This function is called at
board_setup_arch
quoted
quoted
quoted
stage which is earlier than swiotlb_init.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one

arch/powerpc/sysdev/fsl_pci.c |  155
++++++++++++++++++++++++++++++++--
quoted
quoted
-------
quoted
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
I'd like the SWIOTLB refactoring as a separate patch.  Additionally,
the
quoted
quoted
order of patches should be as follows:

1. refactor PCI node parsing code
2. add pci_determine_swiotlb (should rename to
fsl_pci_determine_swiotlb)
quoted
quoted
3. Determine primary bus by looking for ISA node
4. convert all boards over to fsl_pci_init
5. convert fsl pci to platform driver (edac and other fixes should
be
quoted
quoted
quoted
quoted
merged in here)
6. PM support

- k
Should I convert all boards over to fsl_pci_init first and then
convert
quoted
quoted
them
quoted
over to platform driver again or just convert them direct to platform
driver?

Yes do the fsl_pci_init conversion first.  The reason is we should NOT
break functionality from one patch to another.

- k

Actually, the functionality is not broken, other boards just use the
old
quoted
Way to init pci controller and it still works.
=20
How do you figure?  The platform driver is going to get called on boards
not yet converted.  So than you will get 2 different inits of PCI going
on.
=20
- k
In Scott's patch set no platform driver used. fsl_pci_init is just a unifie=
d
routine function for all boards to call. Now other boards in which fsl_pci_=
init
is not called just use the old way to init.

-Hongtao.

RE: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao-B38951 <hidden>
Date: 2012-07-31 06:36:58

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Monday, July 30, 2012 10:47 PM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 30, 2012, at 3:26 AM, Jia Hongtao-B38951 wrote:
=20
quoted
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Saturday, July 28, 2012 5:17 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood Scott-
B07421;
quoted
quoted
Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code


On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
quoted
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
quoted
Hi kumar,

I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done before
probe.
quoted
Another possibility is to try to handle swiotlb init later --
possibly
quoted
quoted
quoted
by reserving memory for it if the platform indicates it's a
possibility
quoted
quoted
quoted
that it will be needed, then freeing the memory if it's not needed.

-Scott
I think the first option seems reasonable.  Can we leave fsl_pci_init(=
)
quoted
quoted
as we now have it and just have the platform driver deal with PM
restore
quoted
quoted
via calling setup_pci_atmu() [probably need to update setup_pci_atmu
to
quoted
quoted
handle restore case, but seems like minor changes]

- k

I think the second option is better if it's hard to decouple swiotlb
determination from pci init. I believe the better architecture that
PCI init in probe function of platform driver will bring us
considerable
quoted
advantage. I really like to keep the completion of pci controller
platform driver not only for PM support but also for pci init.

-Hongtao.
=20
Shifting of swiotlb init has a lot more issues.  Why do we need to do the
PCI init in probe?
=20
- k
I investigated the swiotlb init thing and found that in x86 swiotlb init is
done first and free if we don't need it.

-Hongtao.

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Li Yang <hidden>
Date: 2012-07-31 07:21:23

On Mon, Jul 30, 2012 at 10:46 PM, Kumar Gala [off-list ref] wrote:
On Jul 30, 2012, at 3:26 AM, Jia Hongtao-B38951 wrote:
quoted
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Saturday, July 28, 2012 5:17 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code


On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
quoted
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
quoted
Hi kumar,

I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done before
probe.
quoted
Another possibility is to try to handle swiotlb init later -- possibly
by reserving memory for it if the platform indicates it's a possibility
that it will be needed, then freeing the memory if it's not needed.

-Scott
I think the first option seems reasonable.  Can we leave fsl_pci_init()
as we now have it and just have the platform driver deal with PM restore
via calling setup_pci_atmu() [probably need to update setup_pci_atmu to
handle restore case, but seems like minor changes]

- k

I think the second option is better if it's hard to decouple swiotlb
determination from pci init. I believe the better architecture that
PCI init in probe function of platform driver will bring us considerable
advantage. I really like to keep the completion of pci controller
platform driver not only for PM support but also for pci init.

-Hongtao.
Shifting of swiotlb init has a lot more issues.  Why do we need to do the PCI init in probe?
The ordering issues are introduced by swiotlb.  And the ideal way is
to solve the problem within swiotlb instead of changing PCI to
workaround it.  Take the implementation of x86 as reference it's
possible to be addressed bu allocating first and free later approach.

It is common sense that the initialization of a device is in the probe
function of the driver of the device.  And the change will provide
better unification of PCI controller code.  The PCI controller is
generic enough not to be taken care of at the platform area.

Leo

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Kumar Gala <hidden>
Date: 2012-07-31 13:37:32

On Jul 31, 2012, at 2:21 AM, Li Yang wrote:
On Mon, Jul 30, 2012 at 10:46 PM, Kumar Gala =
[off-list ref] wrote:
quoted
=20
On Jul 30, 2012, at 3:26 AM, Jia Hongtao-B38951 wrote:
=20
quoted
=20
=20
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Saturday, July 28, 2012 5:17 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood =
Scott-B07421;
quoted
quoted
quoted
Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
=20
quoted
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
quoted
Hi kumar,
=20
I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
=20
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done =
before
quoted
quoted
quoted
probe.
quoted
=20
Another possibility is to try to handle swiotlb init later -- =
possibly
quoted
quoted
quoted
quoted
by reserving memory for it if the platform indicates it's a =
possibility
quoted
quoted
quoted
quoted
that it will be needed, then freeing the memory if it's not =
needed.
quoted
quoted
quoted
quoted
=20
-Scott
=20
I think the first option seems reasonable.  Can we leave =
fsl_pci_init()
quoted
quoted
quoted
as we now have it and just have the platform driver deal with PM =
restore
quoted
quoted
quoted
via calling setup_pci_atmu() [probably need to update =
setup_pci_atmu to
quoted
quoted
quoted
handle restore case, but seems like minor changes]
=20
- k
=20
=20
=20
I think the second option is better if it's hard to decouple swiotlb
determination from pci init. I believe the better architecture that
PCI init in probe function of platform driver will bring us =
considerable
quoted
quoted
advantage. I really like to keep the completion of pci controller
platform driver not only for PM support but also for pci init.
=20
-Hongtao.
=20
=20
Shifting of swiotlb init has a lot more issues.  Why do we need to do =
the PCI init in probe?
=20
The ordering issues are introduced by swiotlb.  And the ideal way is
to solve the problem within swiotlb instead of changing PCI to
workaround it.  Take the implementation of x86 as reference it's
possible to be addressed bu allocating first and free later approach.
=20
It is common sense that the initialization of a device is in the probe
function of the driver of the device.  And the change will provide
better unification of PCI controller code.  The PCI controller is
generic enough not to be taken care of at the platform area.
=20
Leo
Than lets look at going with that approach.. Be careful with impact on =
other users of swiotlb on PPC, I believe one 44x board uses swiotlb.

- k=

RE: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Jia Hongtao-B38951 <hidden>
Date: 2012-08-01 02:25:00

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Tuesday, July 31, 2012 9:38 PM
To: Li Yang-R58472
Cc: Jia Hongtao-B38951; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code
=20
=20
On Jul 31, 2012, at 2:21 AM, Li Yang wrote:
=20
quoted
On Mon, Jul 30, 2012 at 10:46 PM, Kumar Gala <galak@kernel.crashing.org=
wrote:
quoted
quoted
On Jul 30, 2012, at 3:26 AM, Jia Hongtao-B38951 wrote:
quoted
quoted
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]
Sent: Saturday, July 28, 2012 5:17 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood Scott-
B07421;
quoted
quoted
quoted
quoted
Li Yang-R58472
Subject: Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie
initialization code


On Jul 27, 2012, at 3:24 PM, Scott Wood wrote:
quoted
On 07/27/2012 05:10 AM, Jia Hongtao-B38951 wrote:
quoted
Hi kumar,

I know "duplicate code from pci_process_bridge_OF_ranges()" is
hard to accept but "refactor the code to have a shared function"
is knotty. Actually this is the reason I didn't do the refactor.
Maybe we should keep doing the init early?  We could still have a
platform device for the PM stuff, but some init would be done
before
quoted
quoted
quoted
quoted
probe.
quoted
Another possibility is to try to handle swiotlb init later --
possibly
quoted
quoted
quoted
quoted
quoted
by reserving memory for it if the platform indicates it's a
possibility
quoted
quoted
quoted
quoted
quoted
that it will be needed, then freeing the memory if it's not needed.

-Scott
I think the first option seems reasonable.  Can we leave
fsl_pci_init()
quoted
quoted
quoted
quoted
as we now have it and just have the platform driver deal with PM
restore
quoted
quoted
quoted
quoted
via calling setup_pci_atmu() [probably need to update setup_pci_atmu
to
quoted
quoted
quoted
quoted
handle restore case, but seems like minor changes]

- k

I think the second option is better if it's hard to decouple swiotlb
determination from pci init. I believe the better architecture that
PCI init in probe function of platform driver will bring us
considerable
quoted
quoted
quoted
advantage. I really like to keep the completion of pci controller
platform driver not only for PM support but also for pci init.

-Hongtao.
Shifting of swiotlb init has a lot more issues.  Why do we need to do
the PCI init in probe?
quoted
The ordering issues are introduced by swiotlb.  And the ideal way is
to solve the problem within swiotlb instead of changing PCI to
workaround it.  Take the implementation of x86 as reference it's
possible to be addressed bu allocating first and free later approach.

It is common sense that the initialization of a device is in the probe
function of the driver of the device.  And the change will provide
better unification of PCI controller code.  The PCI controller is
generic enough not to be taken care of at the platform area.

Leo
=20
Than lets look at going with that approach.. Be careful with impact on
other users of swiotlb on PPC, I believe one 44x board uses swiotlb.
=20
- k
I will be careful with this approach.
I have already noticed 44x. Thank you all the same.

-Hongtao.

Re: [PATCH V3 1/5] powerpc/fsl-pci: Unify pci/pcie initialization code

From: Joakim Tjernlund <hidden>
Date: 2012-08-01 17:49:15


On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
quoted
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function which is architectural better. Also It's convenient for
adding PM support for PCI controller in later patch.

One issue introduced by this architecture is the timing of swiotlb_init.
During PCI initialization the need of swiotlb is determined and this should
be done before swiotlb_init. So a new function to determine swiotlb by
parsing pci ranges is made. This function is called at board_setup_arch
stage which is earlier than swiotlb_init.

Signed-off-by: Jia Hongtao <redacted>
Signed-off-by: Li Yang <redacted>
---
Changed for V3:
- Rebase the patch set on the latest tree
- merge PCI unify and swiotlb patch into one

arch/powerpc/sysdev/fsl_pci.c |  155 ++++++++++++++++++++++++++++++++---------
arch/powerpc/sysdev/fsl_pci.h |    9 +--
2 files changed, 125 insertions(+), 39 deletions(-)
I'd like the SWIOTLB refactoring as a separate patch.  Additionally, the order of patches should be as follows:

1. refactor PCI node parsing code
2. add pci_determine_swiotlb (should rename to fsl_pci_determine_swiotlb)
3. Determine primary bus by looking for ISA node
4. convert all boards over to fsl_pci_init
5. convert fsl pci to platform driver (edac and other fixes should be merged in here)
6. PM support
Could you add:
7. Fix PPC_INDIRECT_TYPE_NO_PCIE_LINK issue. The link is only probed at init and a subsequent
pci/rescan does not change that. See mail thread titled:
  mpc8xxx PCIe hotplug needs fixing, some clues ..

 Jocke
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