On Thu, 2009-11-26 at 09:17 +0100, Gabriel Paubert wrote:

quoted

They should hopefully... as long as you don't rely on the reservation
blowing as a result of a DMA write.

Hmm, this really depends on whether the DMA transfers generate bus cycles
that require coherency or not. Not the other way around. M=1 only forces
bus cycles to be snooped by other processors (asserting the GBL signal
on 603/604/750 busses).

You are absolutely right. Which makes it even more likely that
lwarx/stwcx. won't care unless the L2 cache plays tricks.

The host bridge is free to systematically snoop processor accesses (to make 
sure that data queued in the bridge and not yet written to memory is seen
in the coherent memory domain even if, for example, interrupts propagate 
so fast that DMA target addresses are accessed before it is written to RAM).

On memory coherent systems, the host bridge has to assert the GBL signal,
to force data to be written to memory (for most DMA accesses), or to  
invalidate caches (for full line writes from devices). 

Cheers,
Ben.