[PATCH 19/61] 8xx: Fix CONFIG_PIN_TLB.
From: Scott Wood <hidden>
Date: 2007-07-18 16:30:00
Subsystem:
linux for powerpc (32-bit and 64-bit), the rest · Maintainers:
Madhavan Srinivasan, Linus Torvalds
1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with the default ioremap region. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by: Scott Wood <redacted> --- Apparently I missed sending this one yesterday... arch/powerpc/kernel/head_8xx.S | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 7488f30..c1469f3 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S@@ -701,7 +701,7 @@ initial_mmu: mtspr SPRN_MI_AP, r8 mtspr SPRN_MD_AP, r8 - /* Map another 8 MByte at the IMMR to get the processor + /* Map another 512 KByte at the IMMR to get the processor * internal registers (among other things). */ #ifdef CONFIG_PIN_TLB
@@ -714,7 +714,7 @@ initial_mmu: mr r8, r9 /* Create vaddr for TLB */ ori r8, r8, MD_EVALID /* Mark it valid */ mtspr SPRN_MD_EPN, r8 - li r8, MD_PS8MEG /* Set 8M byte page */ + li r8, MD_PS512K /* Set 512K byte page */ ori r8, r8, MD_SVALID /* Make it valid */ mtspr SPRN_MD_TWC, r8 mr r8, r9 /* Create paddr for TLB */
@@ -736,13 +736,13 @@ initial_mmu: mtspr SPRN_MD_TWC, r9 li r11, MI_BOOTINIT /* Create RPN for address 0 */ addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 #endif /* Since the cache is enabled according to the information we
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1.5.0.3