On 2/20/26 00:35, John Madieu wrote:

Reorder the reset assertion sequence during suspend from
power_resets -> cfg_resets to cfg_resets -> power_resets.
This change ensures the suspend sequence follows the reverse order
of the probe/init sequence, where power_resets are deasserted first
followed by cfg_resets.

Additionally, this ordering is required for RZ/G3E support where
cfg resets are controlled through PCIe AXI registers (offset 0x310h).
According to the RZ/G3E hardware manual (Rev.1.15, section 6.6.6.1.1
"Changing the Initial Values of the Registers"), AXI register access
requires ARESETn to be de-asserted and the clock to be supplied.
Since ARESETn is part of power_resets, cfg_resets must be asserted
before power_resets, otherwise the AXI registers become inaccessible.

For RZ/G3S, both reset types are CPG-controlled, so the order change
has no functional impact.

Please drop this part as the order may impact the functionality. But with this 
fix we now follow the config order from probe, so we should be good now.

Fixes: 7ef502fb35b2 ("PCI: Add Renesas RZ/G3S host controller driver")
Signed-off-by: John Madieu<john.madieu.xa@bp.renesas.com>

With the above addressed:

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>