[PATCH v6 16/16] arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
From: John Madieu <john.madieu.xa@bp.renesas.com>
Date: 2026-02-19 22:37:36
Also in:
linux-clk, linux-pci, linux-renesas-soc
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
The RZ Smarc Crarrier-II board has PCIe slots mounted on it. Enable PCIe support. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- Changes: v6: No changes v5: No changes v4: No changes v3: - Splitted enablement into common carrier dtsi and board dts v2: - Removed board-specific dma-ranges. - Merged enablement and pinmux assignment in same file .../boot/dts/renesas/r9a09g047e57-smarc.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 4 ++++ 2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 696903dc7a63..1ba50512f4ef 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts@@ -122,6 +122,11 @@ key-sleep { #endif }; +&pcie { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; +}; + &pinctrl { canfd_pins: canfd { can1_pins: can1 {
@@ -167,6 +172,17 @@ rsci9_pins: rsci9 { bias-pull-up; }; + pcie-clkreq-n { + gpio-hog; + gpios = <RZG3E_GPIO(4, 5) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "pcie_clkreq_n"; + }; + + pcie_pins: pcie { + pinmux = <RZG3E_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */ + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>;
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index b607b5d6c259..e2a34577a1a1 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi@@ -96,6 +96,10 @@ &i2c0 { clock-frequency = <400000>; }; +&pcie { + status = "okay"; +}; + &scif0 { status = "okay"; };
--
2.25.1