-----Original Message-----
From: John Madieu <john.madieu.xa@bp.renesas.com>
Sent: 19 February 2026 22:36
Subject: [PATCH v6 11/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility

Program the class code register explicitly during PCIe configuration initialization. RZ/G3E requires
this register to be set, while RZ/G3S has these values as hardware defaults.

This configuration is harmless for RZ/G3S where these match the hardware defaults, and necessary for
RZ/G3E to properly identify the device as a PCI bridge.

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v6: Collected Rb tag from Claudiu
v5:
 - Used field_prep for non-constant mask to fix test robot warnings

v4: No changes
v3: No changes
v2: No changes

 drivers/pci/controller/pcie-rzg3s-host.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index c66532a3dae0..f7c23a56da5f 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c

@@ -1065,6 +1065,7 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)  static

int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)  {
 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
+	u32 mask = GENMASK(31, 8);
 	struct resource_entry *ft;
 	struct resource *bus;
 	u8 subordinate_bus;

@@ -1088,6 +1089,13 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
 	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
 	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);

+	/*
+	 * Explicitly program class code. RZ/G3E requires this configuration.
+	 * Harmless for RZ/G3S where this matches the hardware default.
+	 */
+	rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask,