[PATCH v6 15/16] arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
From: John Madieu <john.madieu.xa@bp.renesas.com>
Date: 2026-02-19 22:37:30
Also in:
linux-clk, linux-pci, linux-renesas-soc
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
The RZ/G3E SMARC SoM has a fixed 100 MHz reference clock generator for PCIe. Model it as a fixed-clock and assign it to the PCIe port. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- Changes: v6: No changes v5: No changes v4: No changes v3: No changes v2: No changes arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index eb0de21d6716..7e2345bb9918 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi@@ -43,6 +43,12 @@ memory@48000000 { reg = <0x0 0x48000000 0x0 0xf8000000>; }; + pcie_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V";
@@ -168,6 +174,11 @@ phy1: ethernet-phy@7 { }; }; +&pcie_port0 { + clocks = <&pcie_refclk>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { clk {
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2.25.1