Hi Chanwoo,

On 7/16/19 11:17 AM, Chanwoo Choi wrote:

Hi,

The patch4~patch7 just add the ID to control the clock from DT.
You can squash them to one patch instead of splitting out according to
the type of clock.

Thank you for the review. Yes, you are right it needs to be squashed.

Regards,
Lukasz

On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:

quoted

Add needed IDs to MUXes which are used from DT to properly set clock
hierarchy.

Signed-off-by: Lukasz Luba <redacted>
---
  drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
  1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 361ee53fc9fc..8f1d39cb2f1e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c

@@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
  
  static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
  	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
-	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
+	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
+			SRC_TOP0, 4, 3),
  	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
  			SRC_TOP0, 16, 3),
  	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),

@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
  				TOP_SPARE2, 4, 1),
  
  	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
-	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
+	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
+			SRC_TOP0, 4, 2),
  	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
  			SRC_TOP0, 16, 2),
  	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),

@@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
  
  	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
  			SRC_TOP10, 0, 1),
-	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
-			SRC_TOP10, 4, 1),
+	MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
+			mout_sw_aclk400_mscl_p,	SRC_TOP10, 4, 1),
  	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
  			SRC_TOP10, 8, 1),
  	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,

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