Thread (90 messages) 90 messages, 3 authors, 2019-07-23

Re: [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420

From: Lukasz Luba <hidden>
Date: 2019-07-17 10:27:46
Also in: linux-clk, linux-devicetree, linux-samsung-soc, lkml

On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote:
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba [off-list ref] wrote:
quoted
The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
are not possible to set are removed and new one is added.
I think it is just NOC bus... or are there more of such and this is 100 MHz one?
Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with
3 muxes and one divider), which makes possible to take different PLL as
a source then WCORE have, divide the rate from it and even switch for a
while to alternative stable PLL (on the 2nd mux to SPLL (after a
divider)) to wait for main PLL rate change stability delay. Max rate is
limited to 100MHz for this NOC100 bus.

Regards,
Lukasz
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help