[PATCH v1 18/50] ARM: dts: exynos: add bus_isp with OPP table
From: Lukasz Luba <hidden>
Date: 2019-07-15 12:47:35
Also in:
linux-clk, linux-devicetree, linux-samsung-soc, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
Add bus_isp which controls ACLK400_ISP clock. The OPPs are aligned to parent clock and PLL rate so that the PLL would not need to be reprogrammed. Signed-off-by: Lukasz Luba <redacted> --- arch/arm/boot/dts/exynos5420.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5fb2326875dc..1b717c5c3b1a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi@@ -1095,6 +1095,14 @@ status = "disabled"; }; + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_ISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + bus_wcore_opp_table: opp_table2 { compatible = "operating-points-v2";
@@ -1337,6 +1345,23 @@ opp-hz = /bits/ 64 <400000000>; }; }; + + bus_isp_opp_table: opp_table17 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <150000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + opp02 { + opp-hz = /bits/ 64 <300000000>; + }; + opp03 { + opp-hz = /bits/ 64 <400000000>; + }; + }; }; thermal-zones {
--
2.17.1
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