[PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
From: Lukasz Luba <hidden>
Date: 2019-07-15 12:46:16
Also in:
linux-clk, linux-devicetree, linux-samsung-soc, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
Change the parents of UART clocks to the CPLL which has 666MHz. The UARTs' dividers use /10 rate so they would have 66.6MHz. Signed-off-by: Lukasz Luba <redacted> --- arch/arm/boot/dts/exynos5420.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 18c5273091bd..79f635043247 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi@@ -1486,6 +1486,8 @@ &serial_0 { clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + assigned-clocks = <&clock CLK_MOUT_UART0>; + assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>; dmas = <&pdma0 13>, <&pdma0 14>; dma-names = "rx", "tx"; };
@@ -1493,6 +1495,8 @@ &serial_1 { clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + assigned-clocks = <&clock CLK_MOUT_UART1>; + assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>; dmas = <&pdma1 15>, <&pdma1 16>; dma-names = "rx", "tx"; };
@@ -1500,6 +1504,8 @@ &serial_2 { clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; + assigned-clocks = <&clock CLK_MOUT_UART2>; + assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>; dmas = <&pdma0 15>, <&pdma0 16>; dma-names = "rx", "tx"; };
@@ -1507,6 +1513,8 @@ &serial_3 { clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; + assigned-clocks = <&clock CLK_MOUT_UART3>; + assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>; dmas = <&pdma1 17>, <&pdma1 18>; dma-names = "rx", "tx"; };
--
2.17.1
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