Thread (87 messages) 87 messages, 5 authors, 2018-07-09

[linux-sunxi] Re: [PATCH v3 18/24] drm/sun4i: DW HDMI PHY: Add support for second PLL

From: Chen-Yu Tsai <hidden>
Date: 2018-06-28 06:59:31
Also in: dri-devel, linux-clk, linux-devicetree, lkml

On Thu, Jun 28, 2018 at 12:56 PM, Jernej ?krabec
[off-list ref] wrote:
Dne ?etrtek, 28. junij 2018 ob 04:25:54 CEST je Chen-Yu Tsai napisal(a):
quoted
On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec [off-list ref]
wrote:
quoted
quoted
Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select
between two clock parents.

Add code which reads second PLL from DT.

Signed-off-by: Jernej Skrabec <redacted>
This patch by itself does not do anything. It should be merged with the
next one.
Maxime said clock changes should be separated from DT changes.
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/578775.html
OK. I think the boundary between these two is bit blurred in this case.
And I think implementing support for two or more parents, then actually
adding the second parent makes more sense.

ChenYu
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