[dpdk-dev] [PATCH v15 12/12] config: fix Arm implementer and its SoCs
From: Juraj Linkeš <hidden>
Date: 2021-01-15 13:28:15
Subsystem:
the rest · Maintainer:
Linus Torvalds
Fix the implementer and part number of DPAA and ARMADA SoCs.
The current values of 16 cores and 1 NUMA node don't cover all SoCs from
the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
Increase these to 64 and 4 to widen the coverage.
Add configuration to SoC options where smaller values are needed.
Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms")
Cc: hemant.agrawal@nxp.com
Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a")
Cc: lironh@marvell.com
Fixes: d97108a33231 ("config: change defaults of armv8")
Cc: yskoh@mellanox.com
Signed-off-by: Juraj Linkeš <redacted>
Reviewed-by: Honnappa Nagarahalli <redacted>
---
config/arm/meson.build | 60 +++++++++++++++++++-----------------------
1 file changed, 27 insertions(+), 33 deletions(-)
diff --git a/config/arm/meson.build b/config/arm/meson.build
index eb91e80ff..f6cd7a5e0 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build@@ -60,7 +60,8 @@ part_number_config_arm = { ['RTE_MACHINE', '"neoverse-n1"'], ['RTE_ARM_FEATURE_ATOMICS', true], ['RTE_MAX_MEM_MB', 1048576], - ['RTE_MAX_LCORE', 80] + ['RTE_MAX_LCORE', 80], + ['RTE_MAX_NUMA_NODES', 1] ] }, '0xd49': {
@@ -68,7 +69,8 @@ part_number_config_arm = { 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], ['RTE_ARM_FEATURE_ATOMICS', true], - ['RTE_MAX_LCORE', 64] + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 1] ] } }
@@ -78,8 +80,8 @@ implementer_arm = { ['RTE_MACHINE', '"armv8a"'], ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_LCORE', 16], - ['RTE_MAX_NUMA_NODES', 1] + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 4] ], 'part_number_config': part_number_config_arm }
@@ -147,38 +149,12 @@ implementer_ampere = { } } -implementer_marvell = { - 'description': 'Marvell ARMADA', - 'flags': [ - ['RTE_MACHINE', '"armv8a"'], - ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_LCORE', 16], - ['RTE_MAX_NUMA_NODES', 1] - ], - 'part_number_config': part_number_config_arm -} - -implementer_dpaa = { - 'description': 'NXP DPAA', - 'flags': [ - ['RTE_MACHINE', '"dpaa"'], - ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false], - ['RTE_USE_C11_MEM_MODEL', true], - ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_LCORE', 16], - ['RTE_MAX_NUMA_NODES', 1] - ], - 'part_number_config': part_number_config_arm -} - ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual) implementers = { 'generic': implementer_generic, '0x41': implementer_arm, '0x43': implementer_cavium, - '0x50': implementer_ampere, - '0x56': implementer_marvell, - 'dpaa': implementer_dpaa + '0x50': implementer_ampere } # soc specific aarch64 flags have the highest priority
@@ -191,8 +167,12 @@ soc_generic = { soc_armada = { 'description': 'Marvell ARMADA', - 'implementer': '0x56', + 'implementer': '0x41', 'part_number': '0xd08', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'numa': false, 'disabled_drivers': ['bus/dpaa', 'bus/fslmc', 'common/dpaax'] }
@@ -201,13 +181,23 @@ soc_bluefield = { 'description': 'NVIDIA BlueField', 'implementer': '0x41', 'part_number': '0xd08', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'numa': false } soc_dpaa = { 'description': 'NXP DPAA', - 'implementer': 'dpaa', + 'implementer': '0x41', 'part_number': '0xd08', + 'flags': [ + ['RTE_MACHINE', '"dpaa"'], + ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false], + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'numa': false }
@@ -251,6 +241,10 @@ soc_octeontx2 = { soc_stingray = { 'description': 'Broadcom Stingray', 'implementer': '0x41', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'part_number': '0xd08', 'numa': false }
--
2.20.1