Il 19/02/26 21:49, David Lechner ha scritto:

On 2/2/26 12:28 AM, irving.ch.lin wrote:

quoted

From: Irving-CH Lin <redacted>

Add support for the MT8189 vlpckgen clock controller, which provides
muxes and dividers for clock selection in vlp domain for other IP blocks.

Signed-off-by: Irving-CH Lin <redacted>
---

...

quoted

+static const struct mtk_gate vlp_ck_clks[] = {
+	GATE_VLP_CK(CLK_VLP_CK_VADSYS_VLP_26M_EN, "vlp_vadsys_vlp_26m", "clk26m", 1),
+	GATE_VLP_CK_FLAGS(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, "VLP_fmipi_csi_up26m",

Should "VLP_fmipi_csi_up26m" be all lower-case to match the style of all of
the other clock names? i.e. "vlp_fmipi_csi_up26m"

It *must*. Yes.

Regards,
Angelo

quoted

+			  "osc_d10", 11, CLK_IS_CRITICAL),
+};
+