On 2/19/26 2:44 PM, David Lechner wrote:

On 2/2/26 12:28 AM, irving.ch.lin wrote:

quoted

From: Irving-CH Lin <redacted>

Add support for the MT8189 vlpckgen clock controller, which provides
muxes and dividers for clock selection in vlp domain for other IP blocks.

Signed-off-by: Irving-CH Lin <redacted>
---

quoted

+static const char * const vlp_aud_adc_parents[] = {
+	"clk26m",
+	"vowpll",
+	"aud_adc_ext",

I could not find a matching clock name for "aud_adc_ext" in any
of the other clock drivers. Which clock is this (i.e. what is the
macro name in mediatek,mt8189-clk.h)?

I was able to solve this one. It is a fixed clock. It seems to be
missing from the devicetree, so I will comment there instead.

quoted

+	"osc_d10"
+};
+