On 2/2/26 12:28 AM, irving.ch.lin wrote:

From: Irving-CH Lin <redacted>

Add dt schema and IDs for the clocks of MediaTek MT8189 SoC.
The MT8189 clock IP provide clock control for main system
(apmixedsys, topcksys and vlpcksys) and
subsys (eg. peri, mfg, venc/vdec ...).

+#define CLK_TOP_VOWPLL                                  174

This one seems out of place. It is not used in the driver. It is
a fixed 1:1 divider AFAKCT, so should not be included. (And this
line has spaces while the rest of the file uses tabs for indent.)