[PATCH v5 02/18] clk: mediatek: clk-mux: Make sure bypass clk enabled while setting MFG rate
From: irving.ch.lin <hidden>
Date: 2026-02-02 06:28:57
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: Irving-CH Lin <redacted>
Enable bypass clock before MFG changing rate, to make sure
MFG reference clock available during transient.
Fixes: b66add7a74e8 ("clk: mediatek: mux: add clk notifier functions")
Signed-off-by: Irving-CH Lin <redacted>
---
drivers/clk/mediatek/clk-mux.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
index c5af6dc078a3..07f1f18b38bc 100644
--- a/drivers/clk/mediatek/clk-mux.c
+++ b/drivers/clk/mediatek/clk-mux.c@@ -414,16 +414,21 @@ static int mtk_clk_mux_notifier_cb(struct notifier_block *nb, struct clk_notifier_data *data = _data; struct clk_hw *hw = __clk_get_hw(data->clk); struct mtk_mux_nb *mux_nb = to_mtk_mux_nb(nb); + struct clk_hw *p_hw = clk_hw_get_parent_by_index(hw, mux_nb->bypass_index); int ret = 0; switch (event) { case PRE_RATE_CHANGE: - mux_nb->original_index = mux_nb->ops->get_parent(hw); - ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index); + ret = clk_prepare_enable(p_hw->clk); + if (ret == 0) { + mux_nb->original_index = mux_nb->ops->get_parent(hw); + ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index); + } break; case POST_RATE_CHANGE: case ABORT_RATE_CHANGE: ret = mux_nb->ops->set_parent(hw, mux_nb->original_index); + clk_disable_unprepare(p_hw->clk); break; }
--
2.45.2