Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties
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From: Jie Luo <hidden>
Date: 2023-12-18 03:31:43
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On 12/17/2023 3:08 AM, Russell King (Oracle) wrote:
On Sat, Dec 16, 2023 at 06:30:00PM +0100, Andrew Lunn wrote:quoted
quoted
The following is the chip package, the chip can work on the switch mode like the existed upstream code qca8k, where PHY1-PHY4 is connected with MAC1-MAC4 directly; The chip can also work on the PHY mode, where PHY1- PHY4 is connected with PCS1 by 10g-qxgmii; Either switch mode or PHY mode, the PHY4 is optionally connected with PCS0 by SGMII, PCS0 and PCS1 are connected with the SoC(IPQ platform) PCSes.I don't really understand. Are you saying the hardware is actually : +----------------------------------------------+ | PCS1 PCS0 | | | | MAC0 MAC5 | | | | | | +-----+--------------+-------------+ | | | | | | | Switch | | | | | | | +-+---------+---------+---------+--+ | | | | | | | | MAC1 MAC2 MAC3 MAC4 | | | | PHY1 PHY2 PHY3 PHY4 | +----------------------------------------------+ When in PHY mode, the switch is hard coded to map the 4 PCS1 channels straight to MAC1-MAC4 and all switch functionality is disabled. But then in switch mode, the switch can be controlled as a DSA switch? The 10G PCS1 is then a single 10G port, not 4x 2.5G? Is there a product brief for this PHY? That might help us understand this hardware?Not even digikey give any clues what "QCA8084" is - they list it as "unclassified" and give no documentation and no photo. Basically it seems to be a super secret device.
Sorry for the confusion here, maybe the chip is developed recently, which leads to the Doc or introduction is not released in time.