RE: [PATCH 05/10] ravb: Initialize GbEthernet DMAC

-----Original Message-----
From: Sergei Shtylyov <redacted>
Sent: 04 October 2021 16:51
To: Biju Das <biju.das.jz@bp.renesas.com>; Sergey Shtylyov
[off-list ref]; David S. Miller [off-list ref]; Jakub Kicinski
[off-list ref]
Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Sergey Shtylyov
[off-list ref]; Adam Ford [off-list ref]; Andrew Lunn
[off-list ref]; Yuusuke Ashizuka [off-list ref]; Yoshihiro
Shimoda [off-list ref]; netdev@vger.kernel.org; linux-
renesas-soc@vger.kernel.org; Chris Paterson [off-list ref];
Biju Das [off-list ref]; Prabhakar Mahadev Lad
[off-list ref]
Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC

On 10/4/21 4:12 PM, Biju Das wrote:

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Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC

Hello!

On 10/1/21 6:06 PM, Biju Das wrote:

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Initialize GbEthernet DMAC found on RZ/G2L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
RFC->v1:
 * Removed RIC3 initialization from DMAC init, as it is
   same as reset value.

   I'm not sure we do a reset everytime...

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 * moved stubs function to earlier patches.
 * renamed "rgeth" with "gbeth"
---
 drivers/net/ethernet/renesas/ravb.h      |  3 ++-
 drivers/net/ethernet/renesas/ravb_main.c | 30
+++++++++++++++++++++++-
 2 files changed, 31 insertions(+), 2 deletions(-)

[...]

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diff --git a/drivers/net/ethernet/renesas/ravb_main.c

b/drivers/net/ethernet/renesas/ravb_main.c
index dc817b4d95a1..5790a9332e7b 100644

--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c

@@ -489,7 +489,35 @@ static void ravb_emac_init(struct net_device

*ndev)

 static int ravb_dmac_init_gbeth(struct net_device *ndev)  {
-	/* Place holder */
+	int error;
+
+	error = ravb_ring_init(ndev, RAVB_BE);
+	if (error)
+		return error;
+
+	/* Descriptor format */
+	ravb_ring_format(ndev, RAVB_BE);
+
+	/* Set AVB RX */

   AVB? We don't have it, do we?

Good catch. I Will update the comment in next RFC patch.

   That's trifles, not worth a patch on its own...

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+	ravb_write(ndev, 0x60000000, RCR);

   Not even RCR.EFFS? And what do bits 29..30 mean?

RZ/G2L Bit 31 is reserved.
Bit 16:30 Reception fifo critical level.
Bit 15:1 reserved
Bit 0 : EFFS

I am not sure, where do you get 29..30? can you please clarify.

   0x60000000 has bits 29..30 set and gen3 manual has these bits reserved.

OK.

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[...]

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+	/* Set FIFO size */
+	ravb_write(ndev, 0x00222200, TGC);

   Do TBD<n> (other than TBD0) fields even exist?

Only TBD (Bit 8..9) is available to write,

   Thought so! :-)

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rest all are reserved with remaining values as in "0x00222200"

  Oh, so the defaluts are the sme on RZ/G2L, despite only 1 TX queue?

Yep.

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Regds,
Biju

MBR, Sergey