Re: Route cache performance under stress
From: David S. Miller <hidden>
Date: 2003-06-09 10:03:34
From: Andi Kleen [off-list ref] Date: Mon, 9 Jun 2003 11:47:34 +0200 gcc will generate a lot better code for the memsets if you can tell it somehow they are long aligned and a multiple of 8 bytes. True, but the real bug is that we're initializing any of this crap here at all. Right now we write over the same cachelines 3 or so times. It should really just happen once.