RE: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add support for interrupt handling

-----Original Message-----
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
owner@vger.kernel.org] On Behalf Of Alexander Graf
Sent: Wednesday, July 04, 2012 6:14 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add
support for interrupt handling
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20

quoted

Add bookehv interrupt handling support for 64-bit hosts. Change common

stack

quoted

layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit

execution

quoted

flow to the existing kvm_handler_common asm macro. Update input

register

quoted

values documentation.
Only the bolted version of TLB miss exception handlers is supported

now.

quoted

Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/include/asm/kvm_booke_hv_asm.h |   12 +++-
arch/powerpc/kvm/bookehv_interrupts.S       |  120

+++++++++++++++++++++++++--

quoted

2 files changed, 122 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h

b/arch/powerpc/include/asm/kvm_booke_hv_asm.h

quoted

index 30a600f..8be6f87 100644

--- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
+++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h

@@ -1,5 +1,5 @@

/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as

@@ -17,6 +17,7 @@
 * there are no exceptions for which we fall through directly to
 * the normal host handler.
 *
+ * 32-bit host
 * Expected inputs (normal exceptions):
 *   SCRATCH0 =3D saved r10
 *   r10 =3D thread struct

@@ -33,6 +34,15 @@
 *   *(r8 + GPR9) =3D saved r9
 *   *(r8 + GPR10) =3D saved r10 (r10 not yet clobbered)
 *   *(r8 + GPR11) =3D saved r11
+ *
+ * 64-bit host
+ * Expected inputs (exception types GEN/DBG/CRIT/MC):
+ *  r13 =3D PACA_POINTER
+ *  r10 =3D saved CR
+ *  SPRN_SPRG_##type##_SCRATCH =3D saved r13
+ *  *(r13 + PACA_EX##type + EX_R10) =3D saved r10
+ *  *(r13 + PACA_EX##type + EX_R11) =3D saved r11
+ * Only the bolted version of TLB miss exception handlers is supported

now.

quoted

 */
.macro DO_KVM intno srr1
#ifdef CONFIG_KVM_BOOKE_HV

diff --git a/arch/powerpc/kvm/bookehv_interrupts.S

b/arch/powerpc/kvm/bookehv_interrupts.S

quoted

index dff8ed4..04097de 100644

--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S

@@ -12,10 +12,11 @@
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,

USA.

quoted

 *
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
 *
 * Author: Varun Sethi <varun.sethi@freescale.com>
 * Author: Scott Wood <scotwood@freescale.com>
+ * Author: Mihai Caraman <mihai.caraman@freescale.com>
 *
 * This file is derived from arch/powerpc/kvm/booke_interrupts.S
 */

@@ -30,7 +31,11 @@

#include <asm/bitsperlong.h>
#include <asm/thread_info.h>

+#ifdef CONFIG_64BIT
+#include <asm/exception-64e.h>
+#else
#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
+#endif


+#ifdef CONFIG_64BIT
+/*
+ * For input register values, see

arch/powerpc/include/asm/kvm_booke_hv_asm.h

quoted

+ */
+.macro kvm_handler intno scratch, paca_ex, ex_r10, ex_r11, srr0, srr1,

flags

quoted

+ _GLOBAL(kvmppc_handler_\intno\()_\srr1)

=20
Is this code so vastly different from the 32bit variant that they can't
be the same with a few simple ifdef's here and there?

As you can see from input register values things are quite different. I str=
ived
to keep the code common, the only divergence is in the kvm_handler definiti=
ons.

-Mike