From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:55
This patchset adds 64-bit Book3E PowerPC support to KVM. It is intended
as a request for comment for scratch register changes and for the support
limited to bolted TLB miss exception handlers.
This work was validated on Freescale's e5500 cores using P5020DS boards.
This patchset is based on Alex G. kvm-ppc-next branch. For a ready to use
git tree, please check here:
git://github.com/mcaraman/kvm.git 64-bit-booke
Current limitations:
- 64-bit guests must be configured without KVM support. CPU_FTR_EMB_HV setup
for 64-bit non-hv will be addressed soon in a different patchset.
Prerequisite patches, availabe on top of the git tree:
- commit 7cd1afad10d981cbf4a0c8738bf7f5c0add0e50f:
Make hard_irq_disable() actually hard-disable interrupts
- commit 9a5a0b80cf7e09bd6fadf1a66f27579d0f6d2795, required to run 32-bit
guests on e5500 cores:
powerpc/e5500: Set r5 to point to cpu spec in setup_cpu_e5500()
- commit 6c04342ba5ad7723d8b07d2ad4800607c0985c35, required to run 64-bit
SMP guests:
KVM: PPC: bookehv64: Add support for std/ld emulation
This patchset requires a qemu with e5500 support. For a ready to use git tree,
please check here:
git://repo.or.cz/qemu/agraf.git ppc-e5500
To use qemu run:
$ qemu-system-ppc64 -M mpc8544ds -cpu e5500 -nographic -kernel uImage \
-machine dt_compatible=fsl,,P5020DS
Mike
Mihai Caraman (17):
KVM: PPC64: booke: Set interrupt computation mode for 64-bit host
KVM: PPC64: booke: Add EPCR support in mtspr/mfspr emulation
KVM: PPC64: booke: Add EPCR support in sregs
KVM: PPC64: booke: Add guest computation mode for irq delivery
KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit
KVM: PPC: e500: Add emulation helper for getting instruction ea
KVM: PPC: e500: Mask ea's high 32-bits in 32/64 instr emulation
KVM: PPC: e500mc: Fix tlbilx emulation for 64-bit guests
KVM: PPC64: booke: Hard disable interrupts when entering guest
PowerPC: booke64: Refactor exception prolog for save/restore regs
PowerPC: booke64: Fix machine check handler to use the right prolog
PowerPC: booke64: Add DO_KVM kernel hooks
PowerPC: booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int
KVM: PPC32: bookehv: Remove GET_VCPU macro from exception handler
KVM: PPC64: bookehv: Add support for interrupt handling
KVM: PPC: e500: Silence bogus GCC warning in tlb code
KVM: PPC: booke: Fix get_tb() compile error on 64-bit
arch/powerpc/include/asm/exception-64e.h | 14 ++--
arch/powerpc/include/asm/kvm_booke_hv_asm.h | 12 +++-
arch/powerpc/include/asm/mmu-book3e.h | 2 +-
arch/powerpc/include/asm/reg.h | 6 +-
arch/powerpc/kernel/exceptions-64e.S | 127 ++++++++++++++++++---------
arch/powerpc/kvm/booke.c | 49 +++++++++--
arch/powerpc/kvm/booke.h | 6 ++
arch/powerpc/kvm/booke_emulate.c | 13 +++-
arch/powerpc/kvm/bookehv_interrupts.S | 127 ++++++++++++++++++++++++---
arch/powerpc/kvm/e500.h | 8 +-
arch/powerpc/kvm/e500_emulate.c | 26 +++++-
arch/powerpc/kvm/e500_tlb.c | 28 ++----
arch/powerpc/kvm/e500mc.c | 8 ++-
arch/powerpc/mm/tlb_low_64e.S | 42 +++++----
14 files changed, 347 insertions(+), 121 deletions(-)
--
1.7.4.1
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:49
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
Change get tlb eaddr to use this mask.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/include/asm/mmu-book3e.h | 2 +-
arch/powerpc/kvm/e500.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:50
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the version currently
supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to
keep consitency.
For critical exception handler use SPRG3 instead of SPRG7.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/include/asm/exception-64e.h | 14 +++++++-------
arch/powerpc/include/asm/reg.h | 6 +++---
arch/powerpc/mm/tlb_low_64e.S | 28 ++++++++++++++--------------
3 files changed, 24 insertions(+), 24 deletions(-)
@@ -38,8 +38,11 @@*/-/* We are out of SPRGs so we save some things in the PACA. The normal-*exceptionframeissmallerthantheCRITorMConethough+/* We are out of SPRGs so we save some things in the 8 slots available in PACA.+*ThenormalexceptionframeissmallerthantheCRITorMConethough+*+*BoltedTLBmissexceptionvariantalsousestheseslotswhichincombination+*withpgdandkernel_pgdfitsinone64-bytecacheline.*/#define EX_R1 (0 * 8)#define EX_CR (1 * 8)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:50
Add EPCR support in booke mtspr/mfspr emulation. EPCR register is defined
only for 64-bit and HV categories, so it shoud be available only on 64-bit
virtual processors. Undefine the support for 32-bit builds.
Define a reusable setter function for vcpu's EPCR.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/booke.c | 12 +++++++++++-
arch/powerpc/kvm/booke.h | 6 ++++++
arch/powerpc/kvm/booke_emulate.c | 13 ++++++++++++-
3 files changed, 29 insertions(+), 2 deletions(-)
@@ -759,7 +751,7 @@ int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int rb)tlbilx_all(vcpu_e500,0,pid,rt);tlbilx_all(vcpu_e500,1,pid,rt);}elseif(rt==3){-tlbilx_one(vcpu_e500,pid,ra,rb);+tlbilx_one(vcpu_e500,pid,ea);}returnEMULATE_DONE;
@@ -784,16 +776,13 @@ int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu)returnEMULATE_DONE;}-intkvmppc_e500_emul_tlbsx(structkvm_vcpu*vcpu,intrb)+intkvmppc_e500_emul_tlbsx(structkvm_vcpu*vcpu,gva_tea){structkvmppc_vcpu_e500*vcpu_e500=to_e500(vcpu);intas=!!get_cur_sas(vcpu);unsignedintpid=get_cur_spid(vcpu);intesel,tlbsel;structkvm_book3e_206_tlb_entry*gtlbe=NULL;-gva_tea;--ea=kvmppc_get_gpr(vcpu,rb);for(tlbsel=0;tlbsel<2;tlbsel++){esel=kvmppc_e500_tlb_index(vcpu_e500,ea,tlbsel,pid,as);
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:50
64-bit GCC 4.5.1 warns about an uninitialized variable which was guarded
by a flag. Initialize the variable to make it happy.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/e500_tlb.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:50
64-bit host runs with lazy interrupt disabling, so local_irq_disable() does
not disable interrupts right away and does not protect against preemption
required by __kvmppc_vcpu_run(). Define a macro for 64-bit to use
hard_irq_disable().
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/booke.c | 14 ++++++++++----
1 files changed, 10 insertions(+), 4 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:50
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit booke
see head_fsl_booke.S file. Extend interrupt handlers' parameter list with
interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted version of tlb miss handers is addressed now.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 114 ++++++++++++++++++++++++----------
arch/powerpc/mm/tlb_low_64e.S | 14 +++-
2 files changed, 92 insertions(+), 36 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:51
GET_VCPU define will not be implemented for 64-bit for performance reasons
so get rid of it also on 32-bit.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/bookehv_interrupts.S | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:51
Refactor exception prolog to allow save/restore register parameters. Add
addition none definition for exception prolog usage.
This is needed for exceptions like Guest Doorbell that use GSRRx regsiters
which do not map on exception type.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 23 ++++++++---------------
1 files changed, 8 insertions(+), 15 deletions(-)
@@ -44,54 +44,47 @@addition;/*additionalcodeforthatexc.*/\stdr1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \stwr10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \-mfsprr11,SPRN_##type##_SRR1;/* what are we coming from */ \+mfsprr11,srr1;/*whatarewecomingfrom*/\type##_SET_KSTACK; /* get special stack if necessary */\andi.r10,r11,MSR_PR;/*savestackpointer*/\beq1f;/*brancharoundifsupervisor*/\ldr1,PACAKSAVE(r13);/*getkernelstackcomingfromusr*/\1:cmpdicr1,r1,0;/*checkifSPmakessense*/\bge-cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \-mfsprr10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */+mfsprr10,srr0;/*readSRR0beforetouchingstack*//*Exceptiontype-specificmacros*/#define GEN_SET_KSTACK \subir1,r1,INT_FRAME_SIZE;/*allocframeonkernelstack*/-#define SPRN_GEN_SRR0 SPRN_SRR0-#define SPRN_GEN_SRR1 SPRN_SRR1#define CRIT_SET_KSTACK \ldr1,PACA_CRIT_STACK(r13);\subir1,r1,SPECIAL_EXC_FRAME_SIZE;-#define SPRN_CRIT_SRR0 SPRN_CSRR0-#define SPRN_CRIT_SRR1 SPRN_CSRR1#define DBG_SET_KSTACK \ldr1,PACA_DBG_STACK(r13);\subir1,r1,SPECIAL_EXC_FRAME_SIZE;-#define SPRN_DBG_SRR0 SPRN_DSRR0-#define SPRN_DBG_SRR1 SPRN_DSRR1#define MC_SET_KSTACK \ldr1,PACA_MC_STACK(r13);\subir1,r1,SPECIAL_EXC_FRAME_SIZE;-#define SPRN_MC_SRR0 SPRN_MCSRR0-#define SPRN_MC_SRR1 SPRN_MCSRR1#define NORMAL_EXCEPTION_PROLOG(n, addition) \-EXCEPTION_PROLOG(n,GEN,addition##_GEN(n))+EXCEPTION_PROLOG(n,GEN,SPRN_SRR0,SPRN_SRR1,addition##_GEN(n))#define CRIT_EXCEPTION_PROLOG(n, addition) \-EXCEPTION_PROLOG(n,CRIT,addition##_CRIT(n))+EXCEPTION_PROLOG(n,CRIT,SPRN_CSRR0,SPRN_CSRR1,addition##_CRIT(n))#define DBG_EXCEPTION_PROLOG(n, addition) \-EXCEPTION_PROLOG(n,DBG,addition##_DBG(n))+EXCEPTION_PROLOG(n,DBG,SPRN_DSRR0,SPRN_DSRR1,addition##_DBG(n))#define MC_EXCEPTION_PROLOG(n, addition) \-EXCEPTION_PROLOG(n,MC,addition##_MC(n))+EXCEPTION_PROLOG(n,MC,SPRN_MCSRR0,SPRN_MCSRR1,addition##_MC(n))/*Variantsofthe"addition"argumentfortheprolog*/+#define PROLOG_ADDITION_NONE#define PROLOG_ADDITION_NONE_GEN(n)#define PROLOG_ADDITION_NONE_CRIT(n)#define PROLOG_ADDITION_NONE_DBG(n)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:56
Mask high 32 bits of effective address in emulation layer, for guests running
in 32-bit mode.
MAS2's high-order 32 bits represents the upper 32 bits of the effective address
of the page. Mask it too for tlbwe instruction emulation.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/e500_emulate.c | 5 ++++-
arch/powerpc/kvm/e500_tlb.c | 2 ++
2 files changed, 6 insertions(+), 1 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:57
Add bookehv interrupt handling support for 64-bit hosts. Change common stack
layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit execution
flow to the existing kvm_handler_common asm macro. Update input register
values documentation.
Only the bolted version of TLB miss exception handlers is supported now.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/include/asm/kvm_booke_hv_asm.h | 12 +++-
arch/powerpc/kvm/bookehv_interrupts.S | 120 +++++++++++++++++++++++++--
2 files changed, 122 insertions(+), 10 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:26:59
64-bit host needs to remain in 64-bit mode when an exception take place.
Set interrupt computaion mode in EPCR register.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/e500mc.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:27:01
Machine check exception handler was using a wrong prolog. Hypervisors, like
KVM, which are called early from the exception handler rely on the interrupt
source.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
From: Mihai Caraman <hidden> Date: 2012-06-25 12:27:14
tlbilxva emulation was using an u32 variable for guest effective address.
Replace it with gva_t type to handle 64-bit guests.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/e500mc.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2012-06-26 22:13:01
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
quoted hunk
Refactor exception prolog to allow save/restore register parameters. Add
addition none definition for exception prolog usage.
This is needed for exceptions like Guest Doorbell that use GSRRx regsiters
which do not map on exception type.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 23 ++++++++---------------
1 files changed, 8 insertions(+), 15 deletions(-)
@@ -44,54 +44,47 @@addition;/*additionalcodeforthatexc.*/\stdr1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \stwr10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \-mfsprr11,SPRN_##type##_SRR1;/* what are we coming from */ \+mfsprr11,srr1;/*whatarewecomingfrom*/\type##_SET_KSTACK; /* get special stack if necessary */\andi.r10,r11,MSR_PR;/*savestackpointer*/\beq1f;/*brancharoundifsupervisor*/\ldr1,PACAKSAVE(r13);/*getkernelstackcomingfromusr*/\1:cmpdicr1,r1,0;/*checkifSPmakessense*/\bge-cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \-mfsprr10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */+mfsprr10,srr0;/*readSRR0beforetouchingstack*/
No, use the existing macro, use a ##type## specific to guest doorbells,
with appropriate definitions of the corresponding SPRN_ macros.
Cheers,
Ben.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2012-06-26 22:13:56
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Machine check exception handler was using a wrong prolog. Hypervisors, like
KVM, which are called early from the exception handler rely on the interrupt
source.
Signed-off-by: Mihai Caraman <redacted>
Ack.
Please separate your "core" patches from your KVM series and submit them
separately. I'll take care of the core Book3E part.
Cheers,
Ben.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2012-06-26 22:16:51
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the version currently
supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to
keep consitency.
For critical exception handler use SPRG3 instead of SPRG7.
Beware with SPRG3 usage. It's user space visible and we plan to use it
for other things (see Anton's patch to stick topology information in
there for use by the vdso). If you clobber it, you may want to restore
it later.
I think Anton's patch should put the "proper" value we want in the PACA
anyway since we also need to restore it on exit from KVM, so you can
still use it as scratch, just restore the value before going to C.
Cheers,
Ben.
@@ -38,8 +38,11 @@*/-/* We are out of SPRGs so we save some things in the PACA. The normal-*exceptionframeissmallerthantheCRITorMConethough+/* We are out of SPRGs so we save some things in the 8 slots available in PACA.+*ThenormalexceptionframeissmallerthantheCRITorMConethough+*+*BoltedTLBmissexceptionvariantalsousestheseslotswhichincombination+*withpgdandkernel_pgdfitsinone64-bytecacheline.*/#define EX_R1 (0 * 8)#define EX_CR (1 * 8)
From: Scott Wood <hidden> Date: 2012-06-26 22:24:23
On 06/25/2012 07:26 AM, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the version currently
supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to
keep consitency.
For critical exception handler use SPRG3 instead of SPRG7.
extlb is in the same cache line as other TLB stuff we need, while exgen
isn't. Let's stick with extlb.
-Scott
@@ -1071,6 +1077,11 @@ static int set_sregs_base(struct kvm_vcpu *vcpu,if(!(sregs->u.e.features&KVM_SREGS_E_BASE))return0;+#ifdef CONFIG_64BIT+if(!(sregs->u.e.features&KVM_SREGS_E_64))+return0;+#endif
This means that a QEMU targeting a 32-bit guest won't be able to set any
special registers, if it sets feature bits manually rather than getting
them from GET_SREGS.
This check should only qualify whether we look at sregs.u.e.epcr, not
whether this function works at all.
BTW, shouldn't the BASE check return an error rather than silently no-op?
-Scott
@@ static int set_sregs_base(struct kvm_vcpu *vcpu, if (!(sregs->u.e.features & KVM_SREGS_E_BASE)) return 0;+#ifdef CONFIG_64BIT+ if (!(sregs->u.e.features & KVM_SREGS_E_64))+ return 0;+#endif
This means that a QEMU targeting a 32-bit guest won't be able to set any
special registers, if it sets feature bits manually rather than getting
them from GET_SREGS.
I had some concerns about his. I only check qemu ppc code which uses get/set
approach and I followed the BASE model. Now I see that qemu x86 set them manually :(
Why do we care if the caller set or not BASE?
BASE contains things which should be present on all booke chips. If
that's not set something's wrong.
None of the other feature bits are handled that way.
-Scott
From: Alexander Graf <hidden> Date: 2012-07-04 13:22:55
On 25.06.2012, at 14:26, Mihai Caraman wrote:
64-bit host needs to remain in 64-bit mode when an exception take place.
Set interrupt computaion mode in EPCR register.
Signed-off-by: Mihai Caraman <redacted>
Please split this computation out into its own variable and apply the =
masking regardless. Something like
ulong new_msr =3D vcpu->arch.shared->msr;
if (vcpu->arch.epcr & SPRN_EPCR_ICM)
new_msr |=3D MSR_CM;
new_msr &=3D msr_mask;
kvmppc_set_msr(vcpu, new_msr);
Alex
From: Alexander Graf <hidden> Date: 2012-07-04 13:49:54
On 25.06.2012, at 14:26, Mihai Caraman wrote:
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant =
bits.
Change get tlb eaddr to use this mask.
Please see section 6.11.4.8 in the PowerISA 2.06b:
MMU behavior is largely unaffected by whether the thread is in 32-bit =
computation mode (MSRCM=3D0) or 64- bit computation mode (MSRCM=3D1). =
The only differ- ences occur in the EPN field of the TLB entry and the =
EPN field of MAS2. The differences are summarized here.
=95 Executing a tlbwe instruction in 32-bit mode will set bits =
0:31 of the TLB EPN field to zero unless MAS0ATSEL is set, in which case =
those bits are not written to zero.
=95 In 32-bit implementations, MAS2U can be used to read or =
write EPN0:31 of MAS2.
So if MSR.CM is not set tlbwe should mask the upper 32 bits out - which =
can happen regardless of CONFIG_64BIT.
Also, we need to implement MAS2U, to potentially make the upper 32bits =
of MAS2 available, right? But that one isn't as important as the first =
bit.
Alex
@@ -130,9 +130,9 @@ int kvmppc_e500_emul_mt_mmucsr0(struct =
kvmppc_vcpu_e500 *vcpu_e500,
ulong value);
int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu);
int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu);
-int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb);
-int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, =
ea);
What's the point in hiding ra+rb, but not rt? I like the idea of hiding =
the register semantics, but please move rt into a local variable that =
gets passed as pointer to kvmppc_e500_emul_tlbilx.
Alex
if (ra)
ea +=3D kvmppc_get_gpr(vcpu, ra);
=20
+ if (!(vcpu->arch.shared->msr & MSR_CM))
+ ea &=3D 0xffffffffUL;
=20
Since this will be in generic code, please guard it with an #ifdef =
CONFIG_BOOKE.
Oh and do the same check for MSR_SF on Book3s :). Maybe something like
ulong msr_64bit =3D 0;
#if defined(CONFIG_PPC_BOOK3E_64)
msr_64bit =3D MSR_CM;
#elif defined(CONFIG_PPC_BOOK3S_64)
msr_64bit =3D MSR_SF;
#endif
if (!(vcpu->arch.shared->msr & msr_64bit))
ea =3D (uint32_t)ea;
Alex
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-04 14:14:13
-----Original Message-----
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
owner@vger.kernel.org] On Behalf Of Alexander Graf
Sent: Wednesday, July 04, 2012 4:22 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in
mtspr/mfspr emulation
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Add EPCR support in booke mtspr/mfspr emulation. EPCR register is
defined
quoted
only for 64-bit and HV categories, so it shoud be available only on 64-
bit
quoted
virtual processors. Undefine the support for 32-bit builds.
Define a reusable setter function for vcpu's EPCR.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/booke.c | 12 +++++++++++-
arch/powerpc/kvm/booke.h | 6 ++++++
arch/powerpc/kvm/booke_emulate.c | 13 ++++++++++++-
3 files changed, 29 insertions(+), 2 deletions(-)
=20
Why would the setter be #ifdef CONFIG_64BIT? EPCR exists on e500mc too,
no? Please only #ifdef the GICM bits out.
kvmppc_set_epcr deals with guest EPCR and EPCR does not exist on a virtual =
e500mc
as detailed in patch's comment. All callers are also guarded by #ifdef CONF=
IG_64BIT,
my assumption was that we will not support a virtual core with 64-bit categ=
ory
on a 32-bit host.
=20
=20
Alex
=20
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From: Alexander Graf <hidden> Date: 2012-07-04 14:14:56
On 25.06.2012, at 14:26, Mihai Caraman wrote:
64-bit host runs with lazy interrupt disabling, so local_irq_disable() =
does
not disable interrupts right away and does not protect against =
preemption
quoted hunk
required by __kvmppc_vcpu_run(). Define a macro for 64-bit to use
hard_irq_disable().
=20
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/booke.c | 14 ++++++++++----
1 files changed, 10 insertions(+), 4 deletions(-)
=20
From: Alexander Graf <hidden> Date: 2012-07-04 14:29:58
On 25.06.2012, at 14:26, Mihai Caraman wrote:
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit =
booke
see head_fsl_booke.S file. Extend interrupt handlers' parameter list =
with
interrupt vector numbers to accomodate the macro. Rework Guest =
Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted version of tlb miss handers is addressed now.
=20
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 114 =
#include <asm/ppc-opcode.h>
#include <asm/mmu.h>
#include <asm/hw_irq.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
=20
/* XXX This will ultimately add space for a special exception save
* structure used to save things like SRR0/SRR1, SPRGs, MAS, =
Bleks - this is ugly. Do we really need to open-code the #ifdef here? =
Can't the feature section code determine that the feature is disabled =
and just always not include the code?
+
/* Exception prolog code for all exceptions */
-#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition) =
\
We would we want to pass in 2 numbers? Let's please confine this onto a =
single ID per interrupt vector. Either we use the hardcoded ones =
available here in the KVM code or we use the KVM ones instead of the =
hardcoded ones here. But not both please. Just because it's like that on =
32bit doesn't count as an excuse :).
=20
/* Floating Point Unavailable Interrupt */
START_EXCEPTION(fp_unavailable);
- NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
+ NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
+ PROLOG_ADDITION_NONE)
/* we can probably do a shorter exception entry for that one... =
=20
/* Debug exception as a critical interrupt*/
START_EXCEPTION(debug_crit);
- CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
+ CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
+ PROLOG_ADDITION_2REGS)
=20
/*
* If there is a single step or branch-taken exception in an
@@ -455,7 +485,8 @@ kernel_dbg_exc:
=20
/* Debug exception as a debug interrupt*/
START_EXCEPTION(debug_debug);
- DBG_EXCEPTION_PROLOG(0xd08, PROLOG_ADDITION_2REGS)
+ DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
+ PROLOG_ADDITION_2REGS)
=20
/*
* If there is a single step or branch-taken exception in an
@@ -516,18 +547,21 @@ kernel_dbg_exc:
b .ret_from_except
=20
START_EXCEPTION(perfmon);
- NORMAL_EXCEPTION_PROLOG(0x260, PROLOG_ADDITION_NONE)
+ NORMAL_EXCEPTION_PROLOG(0x260, =
=20
/* Data TLB miss */
START_EXCEPTION(data_tlb_miss_bolted)
- tlb_prolog_bolted SPRN_DEAR
+ tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
=20
/* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
=20
@@ -214,7 +222,7 @@ itlb_miss_fault_bolted:
=20
/* Instruction TLB miss */
START_EXCEPTION(instruction_tlb_miss_bolted)
- tlb_prolog_bolted SPRN_SRR0
+ tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
=20
rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
srdi r15,r16,60 /* get region */
--=20
1.7.4.1
=20
=20
=20
From: Alexander Graf <hidden> Date: 2012-07-04 14:54:02
On 04.07.2012, at 16:14, Caraman Mihai Claudiu-B02008 wrote:
quoted
-----Original Message-----
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
owner@vger.kernel.org] On Behalf Of Alexander Graf
Sent: Wednesday, July 04, 2012 4:22 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in
mtspr/mfspr emulation
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Add EPCR support in booke mtspr/mfspr emulation. EPCR register is
defined
quoted
only for 64-bit and HV categories, so it shoud be available only on =
64-
quoted
bit
quoted
virtual processors. Undefine the support for 32-bit builds.
Define a reusable setter function for vcpu's EPCR.
=20
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/booke.c | 12 +++++++++++-
arch/powerpc/kvm/booke.h | 6 ++++++
arch/powerpc/kvm/booke_emulate.c | 13 ++++++++++++-
3 files changed, 29 insertions(+), 2 deletions(-)
=20
=20
Why would the setter be #ifdef CONFIG_64BIT? EPCR exists on e500mc =
too,
quoted
no? Please only #ifdef the GICM bits out.
=20
kvmppc_set_epcr deals with guest EPCR and EPCR does not exist on a =
virtual e500mc
as detailed in patch's comment. All callers are also guarded by #ifdef =
CONFIG_64BIT,
my assumption was that we will not support a virtual core with 64-bit =
category
on a 32-bit host.
My main concern is that every #ifdef potentially breaks things without =
us knowing. So the less #ifdef's we have, the better off we are. The =
spec only says that we don't _have_ to implement EPCR for non-hv =
non-64bit systems. It doesn't forbid to do so, right?
Alex
/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or =
modify
quoted hunk
* it under the terms of the GNU General Public License, version 2, as
@@ -17,6 +17,7 @@ * there are no exceptions for which we fall through directly to * the normal host handler. *+ * 32-bit host * Expected inputs (normal exceptions): * SCRATCH0 =3D saved r10 * r10 =3D thread struct
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-04 15:27:38
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 5:30 PM
To: Caraman Mihai Claudiu-B02008
Cc: <redacted>; KVM list; linuxppc-dev; qemu-
ppc@nongnu.org List; Benjamin Herrenschmidt
Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
kernel hooks
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit
booke
quoted
see head_fsl_booke.S file. Extend interrupt handlers' parameter list
with
quoted
interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted version of tlb miss handers is addressed now.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 114 ++++++++++++++++++++++++---
#include <asm/ppc-opcode.h>
#include <asm/mmu.h>
#include <asm/hw_irq.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
/* XXX This will ultimately add space for a special exception save
* structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-04 15:37:47
-----Original Message-----
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
owner@vger.kernel.org] On Behalf Of Alexander Graf
Sent: Wednesday, July 04, 2012 6:14 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add
support for interrupt handling
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Add bookehv interrupt handling support for 64-bit hosts. Change common
stack
quoted
layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit
execution
quoted
flow to the existing kvm_handler_common asm macro. Update input
register
quoted
values documentation.
Only the bolted version of TLB miss exception handlers is supported
/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, version 2, as
@@ -17,6 +17,7 @@ * there are no exceptions for which we fall through directly to * the normal host handler. *+ * 32-bit host * Expected inputs (normal exceptions): * SCRATCH0 =3D saved r10 * r10 =3D thread struct
=20
Is this code so vastly different from the 32bit variant that they can't
be the same with a few simple ifdef's here and there?
As you can see from input register values things are quite different. I str=
ived
to keep the code common, the only divergence is in the kvm_handler definiti=
ons.
-Mike
From: Alexander Graf <hidden> Date: 2012-07-04 15:45:10
On 04.07.2012, at 17:27, Caraman Mihai Claudiu-B02008 wrote:
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 5:30 PM
To: Caraman Mihai Claudiu-B02008
Cc: <redacted>; KVM list; linuxppc-dev; qemu-
ppc@nongnu.org List; Benjamin Herrenschmidt
Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add =
DO_KVM
quoted
kernel hooks
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit
booke
quoted
see head_fsl_booke.S file. Extend interrupt handlers' parameter list
with
quoted
interrupt vector numbers to accomodate the macro. Rework Guest =
Doorbell
quoted
quoted
handler to use the proper GSRRx save/restore registers.
Only the bolted version of tlb miss handers is addressed now.
=20
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 114 =
#include <asm/ppc-opcode.h>
#include <asm/mmu.h>
#include <asm/hw_irq.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
=20
/* XXX This will ultimately add space for a special exception save
* structure used to save things like SRR0/SRR1, SPRGs, MAS, =
=20
I agree :) But I opted to keep the optimizations done for 32-bit.
=20
quoted
Do we really need to open-code the #ifdef here?
=20
32-bit implementation fortunately use asm macros, we can't nest =
defines.
=20
quoted
Can't the feature section code determine that the feature is disabled =
and
quoted
just always not include the code?
=20
CPU_FTR_EMB_HV is set even if KVM is not configured.
I don't get the point then. Why not have the whole DO_KVM masked under =
FTR_SECTION_IFSET(CPU_FTR_EMB_HV)? Are there book3s_64 implementations =
without HV? Can't we just mfspr unconditionally in DO_KVM?
=20
quoted
=20
quoted
+
/* Exception prolog code for all exceptions */
-#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)
From: Alexander Graf <hidden> Date: 2012-07-04 15:46:16
On 04.07.2012, at 17:37, Caraman Mihai Claudiu-B02008 wrote:
quoted
-----Original Message-----
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
owner@vger.kernel.org] On Behalf Of Alexander Graf
Sent: Wednesday, July 04, 2012 6:14 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add
support for interrupt handling
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Add bookehv interrupt handling support for 64-bit hosts. Change =
common
quoted
stack
quoted
layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit
execution
quoted
flow to the existing kvm_handler_common asm macro. Update input
register
quoted
values documentation.
Only the bolted version of TLB miss exception handlers is supported
/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or =
modify
quoted
quoted
* it under the terms of the GNU General Public License, version 2, =
as
quoted
quoted
@@ -17,6 +17,7 @@
* there are no exceptions for which we fall through directly to
* the normal host handler.
*
+ * 32-bit host
* Expected inputs (normal exceptions):
* SCRATCH0 =3D saved r10
* r10 =3D thread struct
=0A=
On 04.07.2012, at 17:27, Caraman Mihai Claudiu-B02008 wrote:=0A=
=0A=
quoted
quoted
-----Original Message-----=0A=
From: Alexander Graf [mailto:agraf@suse.de]=0A=
Sent: Wednesday, July 04, 2012 5:30 PM=0A=
To: Caraman Mihai Claudiu-B02008=0A=
Cc: <redacted>; KVM list; linuxppc-dev; qemu-=0A=
ppc@nongnu.org List; Benjamin Herrenschmidt=0A=
Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM=
=0A=
quoted
quoted
kernel hooks=0A=
=0A=
=0A=
On 25.06.2012, at 14:26, Mihai Caraman wrote:=0A=
=0A=
quoted
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit=
=0A=
quoted
quoted
booke=0A=
quoted
see head_fsl_booke.S file. Extend interrupt handlers' parameter list=
=0A=
quoted
quoted
with=0A=
quoted
interrupt vector numbers to accomodate the macro. Rework Guest Doorbel=
l=0A=
quoted
quoted
quoted
handler to use the proper GSRRx save/restore registers.=0A=
Only the bolted version of tlb miss handers is addressed now.=0A=
=0A=
Signed-off-by: Mihai Caraman <redacted>=0A=
---=0A=
arch/powerpc/kernel/exceptions-64e.S | 114 ++++++++++++++++++++++++--=
#include <asm/ppc-opcode.h>=0A=
#include <asm/mmu.h>=0A=
#include <asm/hw_irq.h>=0A=
+#include <asm/kvm_asm.h>=0A=
+#include <asm/kvm_booke_hv_asm.h>=0A=
=0A=
/* XXX This will ultimately add space for a special exception save=0A=
* structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...=
=0A=
I agree :) But I opted to keep the optimizations done for 32-bit.=0A=
=0A=
quoted
Do we really need to open-code the #ifdef here?=0A=
=0A=
32-bit implementation fortunately use asm macros, we can't nest defines.=
=0A=
quoted
=0A=
quoted
Can't the feature section code determine that the feature is disabled a=
nd=0A=
quoted
quoted
just always not include the code?=0A=
=0A=
CPU_FTR_EMB_HV is set even if KVM is not configured.=0A=
=0A=
I don't get the point then. Why not have the whole DO_KVM masked under FTR=
_SECTION_IFSET(CPU_FTR_EMB_HV)? Are there book3s_64 implementations without=
HV? =0A=
=0A=
I guess you refer to book3e_64. I don't know all implementations but Embedd=
ed.HV category is optional.=0A=
=0A=
Can't we just mfspr unconditionally in DO_KVM?=0A=
=0A=
I think Scott should better answer this question, I don't know why he opted=
for the other approach.=0A=
=0A=
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-04 18:22:05
On 04.07.2012, at 17:37, Caraman Mihai Claudiu-B02008 wrote:=0A=
=0A=
quoted
quoted
-----Original Message-----=0A=
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-=0A=
owner@vger.kernel.org] On Behalf Of Alexander Graf=0A=
Sent: Wednesday, July 04, 2012 6:14 PM=0A=
To: Caraman Mihai Claudiu-B02008=0A=
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-=0A=
dev@lists.ozlabs.org; qemu-ppc@nongnu.org=0A=
Subject: Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add=0A=
support for interrupt handling=0A=
=0A=
Is this code so vastly different from the 32bit variant that they can't=
=0A=
quoted
quoted
be the same with a few simple ifdef's here and there?=0A=
=0A=
As you can see from input register values things are quite different. I =
strived=0A=
quoted
to keep the code common, the only divergence is in the kvm_handler defin=
itions.=0A=
=0A=
What a shame :(. A lot of it looks very very similar.=0A=
=0A=
The Devil is in the details ;)=0A=
=0A=
-Mike=
So you only swap out the disable bit, but not the enable one? Ben,
would this work out?
hard_irq_disable() both soft and hard disable. local_irq_enable() will
see that irqs are hard disabled and will hard enable.
However, there's a nastier discrepancy above: local_irq_disable will
properly inform lockdep that we are disabling, while hard_irq_disable
won't.
Arguably we might want to fix that inside hard_irq_disable() itself...
Also you need to be careful. If you are coming with interrupts already
enabled, it's fine, but if you have interrupts soft disabled, then
you hard disable, before you enter the guest you probably want to
check if anything was left "pending" and cancel the entering of the
guest if that is the case.
Cheers,
Ben.
Bleks - this is ugly. Do we really need to open-code the #ifdef here?
Can't the feature section code determine that the feature is disabled
and just always not include the code?
You can't but in any case I don't see the point of the conditional here,
we'll eventually have to load srr1 no ? We can move the load up to here
in all cases or can't we ? If really not, we could have it inside DO_KVM
and be done with it no ?
So if DO_KVM already knows srr1, why explicitly do something with it
the line above, and not in DO_KVM itself?
Yeah that or just move things around in the prolog.
quoted
addition; /* additional code for that exc. */ \
std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
We would we want to pass in 2 numbers? Let's please confine this onto
a single ID per interrupt vector. Either we use the hardcoded ones
available here in the KVM code or we use the KVM ones instead of the
hardcoded ones here. But not both please. Just because it's like that
on 32bit doesn't count as an excuse :).
Right. Also I already objected to the explicit passing of the srr's
anyway.
Cheers,
Ben.
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-05 11:14:40
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 4:50 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
EPN mask for 64-bit
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
Change get tlb eaddr to use this mask.
=20
Please see section 6.11.4.8 in the PowerISA 2.06b:
=20
MMU behavior is largely unaffected by whether the thread is in 32-bit
computation mode (MSRCM=3D0) or 64- bit computation mode (MSRCM=3D1). The
only differ- ences occur in the EPN field of the TLB entry and the EPN
field of MAS2. The differences are summarized here.
=20
* Executing a tlbwe instruction in 32-bit mode will set bits 0:31
of the TLB EPN field to zero unless MAS0ATSEL is set, in which case those
bits are not written to zero.
* In 32-bit implementations, MAS2U can be used to read or write
EPN0:31 of MAS2.
=20
So if MSR.CM is not set tlbwe should mask the upper 32 bits out - which
can happen regardless of CONFIG_64BIT.
MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV =3D 1.0) accordi=
ng
to section 6.10.3.10 in the PowerISA 2.06b.
MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL define
for this case.
Also, we need to implement MAS2U, to potentially make the upper 32bits of
MAS2 available, right? But that one isn't as important as the first bit.
MAS2U is guest privileged why does it need special care?
Freescale core Manuals and EREF does not mention MAS2U so I think I our cas=
e
it is not implemented.
-Mike
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-05 11:40:05
-----Original Message-----
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
owner@vger.kernel.org] On Behalf Of Alexander Graf
Sent: Wednesday, July 04, 2012 4:56 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [RFC PATCH 06/17] KVM: PPC: e500: Add emulation helper for
getting instruction ea
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Add emulation helper for getting instruction ea and refactor tlb
instruction
quoted
emulation to use it.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kvm/e500.h | 6 +++---
arch/powerpc/kvm/e500_emulate.c | 21 ++++++++++++++++++---
arch/powerpc/kvm/e500_tlb.c | 23 ++++++-----------------
3 files changed, 27 insertions(+), 23 deletions(-)
@@ -130,9 +130,9 @@ int kvmppc_e500_emul_mt_mmucsr0(struct
kvmppc_vcpu_e500 *vcpu_e500,
quoted
ulong value);
int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu);
int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu);
-int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb);
-int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int
@@ -82,6 +82,17 @@ static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu
*vcpu, int rb)
quoted
}
#endif
+static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int
ra, int rb)
quoted
+{+ ulong ea;++ ea =3D kvmppc_get_gpr(vcpu, rb);+ if (ra)+ ea +=3D kvmppc_get_gpr(vcpu, ra);++ return ea;+}+
=20
Please move this one to arch/powerpc/include/asm/kvm_ppc.h.
Yep. This is similar with what I had in my internal version before emulatio=
n
refactoring took place upstream. The only difference is that I split the em=
bedded
and server implementation touching this files:
arch/powerpc/include/asm/kvm_booke.h
arch/powerpc/include/asm/kvm_book3s.h
Which approach do you prefer?
=20
quoted
int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
unsigned int inst, int *advance)
{
@@ -89,6 +100,7 @@ int kvmppc_core_emulate_op(struct kvm_run *run,
struct kvm_vcpu *vcpu,
quoted
int ra =3D get_ra(inst);
int rb =3D get_rb(inst);
int rt =3D get_rt(inst);
+ gva_t ea;
switch (get_op(inst)) {
case 31:
@@ -113,15 +125,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run,
struct kvm_vcpu *vcpu,
quoted
break;
case XOP_TLBSX:
- emulated =3D kvmppc_e500_emul_tlbsx(vcpu,rb);
+ ea =3D kvmppc_get_ea_indexed(vcpu, ra, rb);
+ emulated =3D kvmppc_e500_emul_tlbsx(vcpu, ea);
break;
case XOP_TLBILX:
- emulated =3D kvmppc_e500_emul_tlbilx(vcpu, rt, ra, rb);
+ ea =3D kvmppc_get_ea_indexed(vcpu, ra, rb);
+ emulated =3D kvmppc_e500_emul_tlbilx(vcpu, rt, ea);
=20
What's the point in hiding ra+rb, but not rt? I like the idea of hiding
the register semantics, but please move rt into a local variable that
gets passed as pointer to kvmppc_e500_emul_tlbilx.
Why to send it as a pointer? rt which should be rather named t in this case
is an [in] value for tlbilx, according to section 6.11.4.9 in the PowerISA =
2.06b.
-Mike
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-05 11:49:15
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 4:34 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
support in sregs
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
=20
Please also implement a ONE_REG interface while at it. Over time, I'd
like to move towards ONE_REG instead of the messy regs/sregs API.
ONE_REG doesn't seem to be implemented at all for book3e, I looked at
kvm_vcpu_ioctl_set_one_reg/kvm_vcpu_ioctl_get_one_reg in booke.c file.
I can take care of it soon but in a different patch set. It's ok like this?
-Mike
From: Alexander Graf <hidden> Date: 2012-07-05 12:12:37
On 07/05/2012 01:49 PM, Caraman Mihai Claudiu-B02008 wrote:
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 4:34 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
support in sregs
On 25.06.2012, at 14:26, Mihai Caraman wrote:
quoted
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
Please also implement a ONE_REG interface while at it. Over time, I'd
like to move towards ONE_REG instead of the messy regs/sregs API.
ONE_REG doesn't seem to be implemented at all for book3e, I looked at
kvm_vcpu_ioctl_set_one_reg/kvm_vcpu_ioctl_get_one_reg in booke.c file.
I can take care of it soon but in a different patch set. It's ok like this?
Do it in a different patch, but as part of this patch set.
Alex
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-05 12:54:20
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Thursday, July 05, 2012 3:13 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
support in sregs
=20
On 07/05/2012 01:49 PM, Caraman Mihai Claudiu-B02008 wrote:
quoted
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 4:34 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
support in sregs
On 25.06.2012, at 14:26, Mihai Caraman wrote:
quoted
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
Please also implement a ONE_REG interface while at it. Over time, I'd
like to move towards ONE_REG instead of the messy regs/sregs API.
ONE_REG doesn't seem to be implemented at all for book3e, I looked at
kvm_vcpu_ioctl_set_one_reg/kvm_vcpu_ioctl_get_one_reg in booke.c file.
I can take care of it soon but in a different patch set. It's ok like
this?
=20
Do it in a different patch, but as part of this patch set.
Hmm ... then if you don't disagree I will do it as a prerequisite patch sin=
ce I want
to keep this patchset strictly for 64-bit support.
I am not familiar with ONE_REG, is qemu tailored to use it? I need a way to=
test it.
-Mike
Please split this computation out into its own variable and apply the masking regardless. Something like
ulong new_msr = vcpu->arch.shared->msr;
if (vcpu->arch.epcr & SPRN_EPCR_ICM)
new_msr |= MSR_CM;
new_msr &= msr_mask;
kvmppc_set_msr(vcpu, new_msr);
This will fail to clear MSR[CM] in the odd but legal situation where you
have MSR[CM] set but EPCR[ICM] unset.
-Scott
From: Scott Wood <hidden> Date: 2012-07-06 00:19:53
On 07/04/2012 01:15 PM, Caraman Mihai Claudiu-B02008 wrote:
quoted
________________________________________
From: Alexander Graf [agraf@suse.de]
Sent: Wednesday, July 04, 2012 6:45 PM
To: Caraman Mihai Claudiu-B02008
Cc: <redacted>; KVM list; linuxppc-dev; qemu-ppc@nongnu.org List; Benjamin Herrenschmidt
Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks
On 04.07.2012, at 17:27, Caraman Mihai Claudiu-B02008 wrote:
quoted
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 5:30 PM
To: Caraman Mihai Claudiu-B02008
Cc: <redacted>; KVM list; linuxppc-dev; qemu-
ppc@nongnu.org List; Benjamin Herrenschmidt
Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
kernel hooks
On 25.06.2012, at 14:26, Mihai Caraman wrote:
quoted
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit
booke
quoted
see head_fsl_booke.S file. Extend interrupt handlers' parameter list
with
quoted
interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted version of tlb miss handers is addressed now.
Signed-off-by: Mihai Caraman <redacted>
---
arch/powerpc/kernel/exceptions-64e.S | 114 ++++++++++++++++++++++++---
#include <asm/ppc-opcode.h>
#include <asm/mmu.h>
#include <asm/hw_irq.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
/* XXX This will ultimately add space for a special exception save
* structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
I agree :) But I opted to keep the optimizations done for 32-bit.
quoted
Do we really need to open-code the #ifdef here?
32-bit implementation fortunately use asm macros, we can't nest defines.
quoted
Can't the feature section code determine that the feature is disabled and
just always not include the code?
CPU_FTR_EMB_HV is set even if KVM is not configured.
I don't get the point then. Why not have the whole DO_KVM masked under FTR_SECTION_IFSET(CPU_FTR_EMB_HV)? Are there book3s_64 implementations without HV?
I guess you refer to book3e_64. I don't know all implementations but Embedded.HV category is optional.
quoted
Can't we just mfspr unconditionally in DO_KVM?
I think Scott should better answer this question, I don't know why he opted for the other approach.
That was on 32-bit, where some of DO_KVM's users want SRR1 for their own
purposes.
From: Alexander Graf <hidden> Date: 2012-07-06 14:54:44
On 25.06.2012, at 14:26, Mihai Caraman wrote:
tlbilxva emulation was using an u32 variable for guest effective address.
Replace it with gva_t type to handle 64-bit guests.
Signed-off-by: Mihai Caraman <redacted>
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-06 23:03:46
-----Original Message-----
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+mihai.caraman=3Dfreescale.com@lists.ozlabs.org] On Behalf Of
Benjamin Herrenschmidt
Sent: Thursday, July 05, 2012 1:21 AM
To: Alexander Graf
Cc: qemu-ppc@nongnu.org List; Caraman Mihai Claudiu-B02008; linuxppc-dev;
KVM list; [off-list ref]
Subject: Re: [Qemu-ppc] [RFC PATCH 09/17] KVM: PPC64: booke: Hard disable
interrupts when entering guest
=20
On Wed, 2012-07-04 at 16:14 +0200, Alexander Graf wrote:
So you only swap out the disable bit, but not the enable one? Ben,
would this work out?
=20
hard_irq_disable() both soft and hard disable. local_irq_enable() will
see that irqs are hard disabled and will hard enable.
=20
However, there's a nastier discrepancy above: local_irq_disable will
properly inform lockdep that we are disabling, while hard_irq_disable
won't.
=20
Arguably we might want to fix that inside hard_irq_disable() itself...
=20
Also you need to be careful. If you are coming with interrupts already
enabled, it's fine, but if you have interrupts soft disabled, then
you hard disable, before you enter the guest you probably want to
check if anything was left "pending" and cancel the entering of the
guest if that is the case.
On which cases I can find interrupts soft disabled if I call local_irq_enab=
le()
ahead? Can this happen when my kernel task is scheduled?=20
I presume that if I call hard_irq_disable() before entering the guest, a gu=
est exit
will find interrupts soft disabled.
-Mike
From: Alexander Graf <hidden> Date: 2012-07-06 23:11:24
On 07.07.2012, at 00:33, Caraman Mihai Claudiu-B02008 wrote:
quoted
-----Original Message-----
From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
Sent: Thursday, July 05, 2012 1:26 AM
To: Alexander Graf
Cc: Caraman Mihai Claudiu-B02008; <redacted>; KVM =
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-07-07 08:39:47
________________________________________=0A=
From: Alexander Graf [agraf@suse.de]=0A=
Sent: Saturday, July 07, 2012 2:11 AM=0A=
To: Caraman Mihai Claudiu-B02008=0A=
Cc: Benjamin Herrenschmidt; <redacted>; KVM list; linuxppc-=
=0A=
On 07.07.2012, at 00:33, Caraman Mihai Claudiu-B02008 wrote:=0A=
=0A=
quoted
quoted
-----Original Message-----=0A=
From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]=0A=
Sent: Thursday, July 05, 2012 1:26 AM=0A=
To: Alexander Graf=0A=
Cc: Caraman Mihai Claudiu-B02008; <redacted>; KVM list;=
kernel hooks=0A=
=0A=
You can't but in any case I don't see the point of the conditional here=
,=0A=
quoted
quoted
we'll eventually have to load srr1 no ? We can move the load up to here=
=0A=
quoted
quoted
in all cases or can't we ?=0A=
=0A=
I like the idea, but there is a problem with addition macros which may c=
lobber=0A=
quoted
r11 and PROLOG_ADDITION_MASKABLE_GEN is such a case.=0A=
=0A=
Mike -v please :)=0A=
=0A=
Ben suggested something like this:=0A=
=0A=
#define EXCEPTION_PROLOG(n, type, addition) \=0A=
mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \=0A=
mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \=0A=
std r10,PACA_EX##type+EX_R10(r13); \=0A=
std r11,PACA_EX##type+EX_R11(r13); \=0A=
mfcr r10; /* save CR */ \ =0A=
+ mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \=0A=
DO_KVM intnum,srr1; \=0A=
addition; /* additional code for that exc. */ \=0A=
std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \=0A=
stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \=0A=
- mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \=0A=
type##_SET_KSTACK; /* get special stack if necessary */\=0A=
andi. r10,r11,MSR_PR; /* save stack pointer */ \=0A=
=0A=
But one of the addition looks like this:=0A=
=0A=
#define PROLOG_ADDITION_MASKABLE_GEN(n) \=0A=
lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \=0A=
cmpwi cr0,r11,0; /* yes -> go out of line */ \=0A=
beq masked_interrupt_book3e_##n =0A=
=0A=
So for maskable gen we end up with:=0A=
=0A=
#define EXCEPTION_PROLOG(n, type, addition) \=0A=
mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \=0A=
mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \=0A=
std r10,PACA_EX##type+EX_R10(r13); \=0A=
std r11,PACA_EX##type+EX_R11(r13); \=0A=
mfcr r10; /* save CR */ \=0A=
mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \=0A=
DO_KVM intnum,srr1; \=0A=
lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \=0A=
cmpwi cr0,r11,0; /* yes -> go out of line */ \=0A=
beq masked_interrupt_book3e_##n \=0A=
std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \=0A=
stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \=0A=
type##_SET_KSTACK; /* get special stack if necessary */\=0A=
andi. r10,r11,MSR_PR; /* save stack pointer */ \=0A=
=0A=
This affects the last asm line, we load srr1 into r11 but clobber it in-bet=
ween.=0A=
We need a spare register for maskable gen addition. I think we can free r10=
sooner=0A=
and used it in addition like this:=0A=
=0A=
#define EXCEPTION_PROLOG(n, type, addition) \=0A=
mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \=0A=
mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ =0A=
std r10,PACA_EX##type+EX_R10(r13); \=0A=
std r11,PACA_EX##type+EX_R11(r13); \=0A=
+ mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \=0A=
mfcr r10; /* save CR */ \=0A=
+ stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \=0A=
DO_KVM intnum,srr1; \=0A=
- lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \=0A=
- cmpwi cr0,r11,0; /* yes -> go out of line */ \=0A=
+ lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \=0A=
+ cmpwi cr0,r10,0; /* yes -> go out of line */ \=0A=
beq masked_interrupt_book3e_##n \=0A=
std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \=0A=
- stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \=0A=
- mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \=0A=
type##_SET_KSTACK; /* get special stack if necessary */\=0A=
andi. r10,r11,MSR_PR; /* save stack pointer */ \=0A=
=0A=
-Mike=
@@ -130,9 +130,9 @@ int kvmppc_e500_emul_mt_mmucsr0(struct
kvmppc_vcpu_e500 *vcpu_e500,
quoted
ulong value);
int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu);
int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu);
-int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int =
rb);
quoted
quoted
-int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, =
int
quoted
rb);
quoted
-int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb);+int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, gva_t ea);+int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, gva_t =
+{+ ulong ea;++ ea =3D kvmppc_get_gpr(vcpu, rb);+ if (ra)+ ea +=3D kvmppc_get_gpr(vcpu, ra);++ return ea;+}+
=20
Please move this one to arch/powerpc/include/asm/kvm_ppc.h.
=20
Yep. This is similar with what I had in my internal version before =
emulation
refactoring took place upstream. The only difference is that I split =
the embedded
and server implementation touching this files:
arch/powerpc/include/asm/kvm_booke.h
arch/powerpc/include/asm/kvm_book3s.h
=20
Which approach do you prefer?
This is generic code to me, so it shouldn't go into booke/book3s =
specific files.
=20
quoted
=20
quoted
int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu =
*vcpu,
quoted
quoted
unsigned int inst, int *advance)
{
@@ -89,6 +100,7 @@ int kvmppc_core_emulate_op(struct kvm_run *run,
struct kvm_vcpu *vcpu,
quoted
int ra =3D get_ra(inst);
int rb =3D get_rb(inst);
int rt =3D get_rt(inst);
+ gva_t ea;
=20
switch (get_op(inst)) {
case 31:
@@ -113,15 +125,18 @@ int kvmppc_core_emulate_op(struct kvm_run =
*run,
quoted
struct kvm_vcpu *vcpu,
quoted
break;
=20
case XOP_TLBSX:
- emulated =3D kvmppc_e500_emul_tlbsx(vcpu,rb);
+ ea =3D kvmppc_get_ea_indexed(vcpu, ra, rb);
+ emulated =3D kvmppc_e500_emul_tlbsx(vcpu, ea);
break;
=20
case XOP_TLBILX:
- emulated =3D kvmppc_e500_emul_tlbilx(vcpu, rt, =
=20
What's the point in hiding ra+rb, but not rt? I like the idea of =
hiding
quoted
the register semantics, but please move rt into a local variable that
gets passed as pointer to kvmppc_e500_emul_tlbilx.
=20
Why to send it as a pointer? rt which should be rather named t in this =
case
is an [in] value for tlbilx, according to section 6.11.4.9 in the =
PowerISA 2.06b.
Because usually rt in the PPC ISA denotes a _t_arget _r_egister. The =
field here really is called "T" to denote the _t_ype of the operation =
which you correctly pointed out. Could you please change this misnaming =
along the way and mask it accordingly?
Alex
From: Alexander Graf <hidden> Date: 2012-07-11 22:25:27
On 07.07.2012, at 10:39, Caraman Mihai Claudiu-B02008 wrote:
quoted
________________________________________
From: Alexander Graf [agraf@suse.de]
Sent: Saturday, July 07, 2012 2:11 AM
To: Caraman Mihai Claudiu-B02008
Cc: Benjamin Herrenschmidt; <redacted>; KVM list; =
=20
On 07.07.2012, at 00:33, Caraman Mihai Claudiu-B02008 wrote:
=20
quoted
quoted
-----Original Message-----
From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
Sent: Thursday, July 05, 2012 1:26 AM
To: Alexander Graf
Cc: Caraman Mihai Claudiu-B02008; <redacted>; KVM =
kernel hooks
=20
You can't but in any case I don't see the point of the conditional =
here,
quoted
quoted
quoted
we'll eventually have to load srr1 no ? We can move the load up to =
here
quoted
quoted
quoted
in all cases or can't we ?
=20
I like the idea, but there is a problem with addition macros which =
may clobber
quoted
quoted
r11 and PROLOG_ADDITION_MASKABLE_GEN is such a case.
=20
Mike -v please :)
=20
Ben suggested something like this:
=09
#define EXCEPTION_PROLOG(n, type, addition) \
mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ =
\
mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
std r10,PACA_EX##type+EX_R10(r13); \
std r11,PACA_EX##type+EX_R11(r13); \
mfcr r10; /* save CR */ \=09
+ mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
DO_KVM intnum,srr1; \
addition; /* additional code for that exc. */ \
std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ =
\
- mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
type##_SET_KSTACK; /* get special stack if necessary */\
andi. r10,r11,MSR_PR; /* save stack pointer */ \
=20
But one of the addition looks like this:
=09
#define PROLOG_ADDITION_MASKABLE_GEN(n) \
lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
cmpwi cr0,r11,0; /* yes -> go out of line */ \
beq masked_interrupt_book3e_##n=09
=20
So for maskable gen we end up with:
=20
#define EXCEPTION_PROLOG(n, type, addition) \
mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ =
\
mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
std r10,PACA_EX##type+EX_R10(r13); \
std r11,PACA_EX##type+EX_R11(r13); \
mfcr r10; /* save CR */ \
mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
DO_KVM intnum,srr1; \
lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
cmpwi cr0,r11,0; /* yes -> go out of line */ \
beq masked_interrupt_book3e_##n \
std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ =
\
type##_SET_KSTACK; /* get special stack if necessary */\
andi. r10,r11,MSR_PR; /* save stack pointer */ \
=09
This affects the last asm line, we load srr1 into r11 but clobber it =
in-between.
We need a spare register for maskable gen addition. I think we can =
Or just free up another register early on, like here.
Alex
+ mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
mfcr r10; /* save CR */ \
+ stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ =
\
DO_KVM intnum,srr1; \
- lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
- cmpwi cr0,r11,0; /* yes -> go out of line */ \
+ lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
+ cmpwi cr0,r10,0; /* yes -> go out of line */ \
beq masked_interrupt_book3e_##n \
std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
- stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ =
\
- mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
type##_SET_KSTACK; /* get special stack if necessary */\
andi. r10,r11,MSR_PR; /* save stack pointer */ \
=09
-Mike
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From: Alexander Graf <hidden> Date: 2012-07-11 22:52:04
On 12.07.2012, at 00:43, Benjamin Herrenschmidt wrote:
On Thu, 2012-07-12 at 00:35 +0200, Alexander Graf wrote:
quoted
quoted
On Thu, 2012-07-12 at 00:25 +0200, Alexander Graf wrote:
quoted
Or just free up another register early on, like here.
=20
If you're going to do that, you want to measure the impact on null
syscall performance though.
=20
That should hold true for any change in that code, no?
=20
Yes, but adding a gpr save is more invasive (you have to also load it
back later on & put it on the stack).
What's the usual cache line size like on these boxes? If you align it =
properly with r10 and r11 on the paca so that all 3 registers are in the =
same cache line, the load should be almost for free, no?
Alex
From: Alexander Graf <hidden> Date: 2012-10-08 10:10:49
On 05.07.2012, at 13:14, Caraman Mihai Claudiu-B02008 wrote:
=20
=20
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 4:50 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend =
MAS2
quoted
EPN mask for 64-bit
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant =
bits.
quoted
quoted
Change get tlb eaddr to use this mask.
=20
Please see section 6.11.4.8 in the PowerISA 2.06b:
=20
MMU behavior is largely unaffected by whether the thread is in 32-bit
computation mode (MSRCM=3D0) or 64- bit computation mode (MSRCM=3D1). =
The
quoted
only differ- ences occur in the EPN field of the TLB entry and the =
EPN
quoted
field of MAS2. The differences are summarized here.
=20
* Executing a tlbwe instruction in 32-bit mode will set bits =
0:31
quoted
of the TLB EPN field to zero unless MAS0ATSEL is set, in which case =
those
quoted
bits are not written to zero.
* In 32-bit implementations, MAS2U can be used to read or write
EPN0:31 of MAS2.
=20
So if MSR.CM is not set tlbwe should mask the upper 32 bits out - =
which
quoted
can happen regardless of CONFIG_64BIT.
=20
MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV =3D 1.0) =
according
to section 6.10.3.10 in the PowerISA 2.06b.
=20
MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL =
define
for this case.
So tlbe->mas2 is guaranteed to have the upper bits be 0 when MSR.CM=3D0?
=20
quoted
Also, we need to implement MAS2U, to potentially make the upper =
32bits of
quoted
MAS2 available, right? But that one isn't as important as the first =
bit.
=20
MAS2U is guest privileged why does it need special care?
Maybe it's mapped to the upper bits of GMAS2 automatically?
Freescale core Manuals and EREF does not mention MAS2U so I think I =
our case
it is not implemented.
Please check with a simple mfspr() test on real hw to see if it really =
isn't implemented.
Alex
From: Caraman Mihai Claudiu-B02008 <hidden> Date: 2012-10-08 13:06:44
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Monday, October 08, 2012 1:11 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
EPN mask for 64-bit
=20
=20
On 05.07.2012, at 13:14, Caraman Mihai Claudiu-B02008 wrote:
=20
quoted
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 4:50 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
EPN mask for 64-bit
On 25.06.2012, at 14:26, Mihai Caraman wrote:
quoted
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant
bits.
quoted
quoted
quoted
Change get tlb eaddr to use this mask.
Please see section 6.11.4.8 in the PowerISA 2.06b:
MMU behavior is largely unaffected by whether the thread is in 32-bit
computation mode (MSRCM=3D0) or 64- bit computation mode (MSRCM=3D1). =
The
quoted
quoted
only differ- ences occur in the EPN field of the TLB entry and the EPN
field of MAS2. The differences are summarized here.
* Executing a tlbwe instruction in 32-bit mode will set bits 0:31
of the TLB EPN field to zero unless MAS0ATSEL is set, in which case
those
quoted
quoted
bits are not written to zero.
* In 32-bit implementations, MAS2U can be used to read or write
EPN0:31 of MAS2.
So if MSR.CM is not set tlbwe should mask the upper 32 bits out -
which
quoted
quoted
can happen regardless of CONFIG_64BIT.
MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV =3D 1.0)
according
quoted
to section 6.10.3.10 in the PowerISA 2.06b.
MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL
define
quoted
for this case.
=20
So tlbe->mas2 is guaranteed to have the upper bits be 0 when MSR.CM=3D0?
We chose to mask out mas2 upper bits on tlbwe emulation so gtlbe->mas2 will
respect this but vcpu->arch.shared->mas2 will not. tlb entry selection does=
not
require this treatment since EPN upper bits are not taken into consideratio=
n anyway.
=20
quoted
quoted
Also, we need to implement MAS2U, to potentially make the upper 32bits
of
quoted
quoted
MAS2 available, right? But that one isn't as important as the first
bit.
quoted
MAS2U is guest privileged why does it need special care?
=20
Maybe it's mapped to the upper bits of GMAS2 automatically?
GMAS2?
=20
quoted
Freescale core Manuals and EREF does not mention MAS2U so I think I our
case
quoted
it is not implemented.
=20
Please check with a simple mfspr() test on real hw to see if it really
isn't implemented.
From: Alexander Graf <hidden> Date: 2012-10-08 13:10:48
On 08.10.2012, at 15:06, Caraman Mihai Claudiu-B02008 wrote:
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Monday, October 08, 2012 1:11 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend =
MAS2
quoted
EPN mask for 64-bit
=20
=20
On 05.07.2012, at 13:14, Caraman Mihai Claudiu-B02008 wrote:
=20
quoted
=20
=20
quoted
-----Original Message-----
From: Alexander Graf [mailto:agraf@suse.de]
Sent: Wednesday, July 04, 2012 4:50 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
dev@lists.ozlabs.org; qemu-ppc@nongnu.org
Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend =
MAS2
quoted
quoted
quoted
EPN mask for 64-bit
=20
=20
On 25.06.2012, at 14:26, Mihai Caraman wrote:
=20
quoted
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant
bits.
quoted
quoted
quoted
Change get tlb eaddr to use this mask.
=20
Please see section 6.11.4.8 in the PowerISA 2.06b:
=20
MMU behavior is largely unaffected by whether the thread is in =
32-bit
quoted
quoted
quoted
computation mode (MSRCM=3D0) or 64- bit computation mode (MSRCM=3D1).=
The
quoted
quoted
quoted
only differ- ences occur in the EPN field of the TLB entry and the =
EPN
quoted
quoted
quoted
field of MAS2. The differences are summarized here.
=20
* Executing a tlbwe instruction in 32-bit mode will set bits =
0:31
quoted
quoted
quoted
of the TLB EPN field to zero unless MAS0ATSEL is set, in which case
those
quoted
quoted
bits are not written to zero.
* In 32-bit implementations, MAS2U can be used to read or write
EPN0:31 of MAS2.
=20
So if MSR.CM is not set tlbwe should mask the upper 32 bits out -
which
quoted
quoted
can happen regardless of CONFIG_64BIT.
=20
MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV =3D 1.0)
according
quoted
to section 6.10.3.10 in the PowerISA 2.06b.
=20
MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL
define
quoted
for this case.
=20
So tlbe->mas2 is guaranteed to have the upper bits be 0 when =
MSR.CM=3D0?
=20
We chose to mask out mas2 upper bits on tlbwe emulation so gtlbe->mas2 =
will
respect this but vcpu->arch.shared->mas2 will not. tlb entry selection =
does not
require this treatment since EPN upper bits are not taken into =
consideration anyway.
That's fine. We don't control the contents of shared->mas2 anyway.
=20
quoted
=20
quoted
=20
quoted
Also, we need to implement MAS2U, to potentially make the upper =
32bits
quoted
of
quoted
quoted
MAS2 available, right? But that one isn't as important as the first
bit.
quoted
=20
MAS2U is guest privileged why does it need special care?
=20
Maybe it's mapped to the upper bits of GMAS2 automatically?
=20
GMAS2?
Ah. The guest has direct control over the real MAS2. Oh well.
=20
quoted
=20
quoted
Freescale core Manuals and EREF does not mention MAS2U so I think I =
our
quoted
case
quoted
it is not implemented.
=20
Please check with a simple mfspr() test on real hw to see if it =