Re: [PATCH v3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

On 08/22/2011 10:25 AM, Ivan Djelic wrote:

Did you take into account the fact that because MTD thinks this a 2K chip,
you will have to wait twice for the nand busy read time (typically 25 us) per
each 4K read. In other words, to read 4 kBytes you will do:

1. send read0 (00), send address, send read1 (30)
2. wait tRB
3. transfer 2 kBytes
4. send read0 (00), send address, send read1 (30)
5. wait tRB
6. transfer 2 kBytes

Same problem for writes (but rather 100 us instead of 25 us).

How does that compare with hw ecc gain in terms of performance ?

We'd have the double-delay with the sw ecc plus buffering approach as well.

To eliminate it we'd need to do an extra data transfer without reissuing
the command, which Shuo was unable to get to work.

And it's not worse than having an actual 2K chip. :-)

-Scott