Re: [PATCH v3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

On 08/19/2011 03:57 AM, Matthieu CASTET wrote:

LiuShuo a =C3=A9crit :

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=E4=BA=8E 2011=E5=B9=B408=E6=9C=8819=E6=97=A5 01:00, Matthieu CASTET =E5=

=86=99=E9=81=93:

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b35362@freescale.com a =C3=A9crit :

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From: Liu Shuo<redacted>

Freescale FCM controller has a 2K size limitation of buffer RAM. In =

order

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to support the Nand flash chip whose page size is larger than 2K byt=

es,

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we divide a page into multi-2K pages for MTD layer driver. In that c=

ase,

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we force to set the page size to 2K bytes. We convert the page addre=

ss of

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MTD layer driver to a real page address in flash chips and a column =

index

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in fsl_elbc driver. We can issue any column address by UA instructio=

n of

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elbc controller.

Why do you need to do that ?

When mtd send you a 4k page, why can't you write it by 2*2k pages wri=

te ?

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1. It's easy to implement.
2. We don't need to move the data in buffer more times, because we
want to use the HW_ECC.

In flash chip per Page:
----------------------------------------------------------------
| first data | first oob | second data | second oob |
----------------------------------------------------------------

How the bad block marker are handled with this remapping ?

It has to be migrated prior to first use (this needs to be documented,
and ideally a U-Boot command provided do do this), or else special
handling would be needed when building the BBT.  The only way around
this would be to do ECC in software, and do the buffering needed to let
MTD treat it as a 4K chip.

-Scott