Re: [PATCH v3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
From: Artem Bityutskiy <dedekind1@gmail.com>
Date: 2011-08-22 10:56:51
On Fri, 2011-08-19 at 13:10 -0500, Scott Wood wrote:
On 08/19/2011 03:57 AM, Matthieu CASTET wrote:quoted
LiuShuo a écrit :quoted
于 2011年08月19日 01:00, Matthieu CASTET 写道:quoted
b35362@freescale.com a écrit :quoted
From: Liu Shuo<redacted> Freescale FCM controller has a 2K size limitation of buffer RAM. In order to support the Nand flash chip whose page size is larger than 2K bytes, we divide a page into multi-2K pages for MTD layer driver. In that case, we force to set the page size to 2K bytes. We convert the page address of MTD layer driver to a real page address in flash chips and a column index in fsl_elbc driver. We can issue any column address by UA instruction of elbc controller.Why do you need to do that ? When mtd send you a 4k page, why can't you write it by 2*2k pages write ?1. It's easy to implement. 2. We don't need to move the data in buffer more times, because we want to use the HW_ECC. In flash chip per Page: ---------------------------------------------------------------- | first data | first oob | second data | second oob | ----------------------------------------------------------------How the bad block marker are handled with this remapping ?It has to be migrated prior to first use (this needs to be documented, and ideally a U-Boot command provided do do this), or else special handling would be needed when building the BBT. The only way around this would be to do ECC in software, and do the buffering needed to let MTD treat it as a 4K chip.
It really feels like a special hack which would better not go to mainline - am I the only one with such feeling? If yes, probably I am wrong... -- Best Regards, Artem Bityutskiy