On Thu, 2011-05-19 at 22:02 -0500, Kazutomo Yoshii wrote:

On 05/19/2011 09:13 PM, Benjamin Herrenschmidt wrote:

quoted

On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:
   

quoted

On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
     

quoted

Actually DMA sends invalidate requests to the snoop unit(L2 level).
BGP SoC is a bit different from other 4xx base.
       

Well, some other 44x also have a snooping L2 (more or less), but L1 is
usually the problem.
     

Hrm... looking at the doco you pointed me to, it looks like the L1 -is-
coherent, it gets snoop kills from the L2.
   

Right, L1D is coherent if write throug is set.
L1I(virtually tagged) is not coherent, btw.

Yes, I wrote the horrid hack to ping pong the pages between writable and
executable afaik :-)

quoted

Ok so we do need to make this non-coherent cache stuff a runtime option
(well, we need that for 440+476 too anyways so may as well do it now).
   

What sort of runtime option do you mean?

I've asked Tony to give it a go since he's taking over the 476 stuff.
The idea is to make it a MMU feature and call into the cache flush
conditionally on it rather than under the control of a ifdef.

I want it to be possible to build a unified kernel that supports
multiple 44x and 47x platforms including BGP if we can make it happen.

There's still some roadblocks to support 47x and 44x in the same kernel,
most notably the cache line size, but I have hopes I'll get Tony to fix
them soon :-)

Cheers,
Ben.

- kaz

quoted

As for the alignment of kmalloc, it looks like a hack that should be
done in the torus code itself.

Cheers,
Ben.

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