On Thu, 2011-05-19 at 19:47 -0500, Eric Van Hensbergen wrote:

On Thu, May 19, 2011 at 7:36 PM, Benjamin Herrenschmidt
[off-list ref] wrote:

quoted

On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:

quoted

-#ifdef CONFIG_NOT_COHERENT_CACHE
+#if defined(CONFIG_NOT_COHERENT_CACHE) || defined(CONFIG_BGP)
 #define ARCH_DMA_MINALIGN    L1_CACHE_BYTES
 #endif

Is DMA cache coherent on BG/P ? That's odd for a 4xx base :-)

My understanding of things (which could be totally wrong) is that the
DMA we care about on BG/P (namely the Torus and Collective networks)
is coherent at the L2.  Of course the change in question is talking
about L1_CACHE_BYTES, so my reading of this is that its a sleazy way
of getting aligned mallocs that make interactions with the tightly
coupled networks easier/more-efficient.  I'm open to alternative
suggestions.

But if it's not coherent with L1, then you sould have
CONFIG_NOT_COHERENT_CACHE set and not need that patch... or am I missing
something ?

One thing we should do some day as well is make that whole non-coherent
be runtime selected, on the list of things to fix 440+47x in the same
kernel. Pfiew....

Cheers,
Ben.