On Fri, May 08, 2020 at 06:31:34PM +0100, Mark Brown wrote:

On Fri, May 08, 2020 at 04:29:33PM +0300, Serge Semin wrote:

quoted

If DMAC register is left uncleared any further DMAless transfers
may cause the DMAC hardware handshaking interface getting activated.
So the next DMA-based Rx/Tx transaction will be started right
after the dma_async_issue_pending() method is invoked even if no
DMATDLR/DMARDLR conditions are met. This at the same time may cause
the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
must clear DMAC register after a current DMA-based transaction is
finished.

This also looks like a bugfix so should be pulled forwards to the start
of the series if possible.

Ok.

-Sergey