[PATCH RFC 02/67] MIPS: Add cases for CPU_QEMUR6
From: Markos Chandras <hidden>
Date: 2014-12-18 15:11:08
Subsystem:
mips, the rest · Maintainers:
Thomas Bogendoerfer, Linus Torvalds
From: Leonid Yegoshin <redacted> Add a CPU_QEMUR6 case to various switch statements. Signed-off-by: Leonid Yegoshin <redacted> Signed-off-by: Markos Chandras <redacted> --- arch/mips/include/asm/cpu-type.h | 5 +++++ arch/mips/kernel/idle.c | 1 + arch/mips/kernel/spram.c | 1 + arch/mips/kernel/traps.c | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/sc-mips.c | 1 + arch/mips/mm/tlbex.c | 1 + 7 files changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index b4e2bd87df50..68fb94592ae3 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h@@ -54,6 +54,11 @@ static inline int __pure __get_cpu_type(const int cpu_type) case CPU_M5150: #endif +#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \ + defined(CONFIG_SYS_HAS_CPU_MIPS64_R6) + case CPU_QEMUR6: +#endif + #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 case CPU_5KC: case CPU_5KE:
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 0b9082b6b683..8abb7336a3d0 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c@@ -186,6 +186,7 @@ void __init check_wait(void) case CPU_PROAPTIV: case CPU_P5600: case CPU_M5150: + case CPU_QEMUR6: cpu_wait = r4k_wait; if (read_c0_config7() & MIPS_CONF7_WII) cpu_wait = r4k_wait_irqoff;
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 67f2495def1c..35dbad02b040 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c@@ -208,6 +208,7 @@ void spram_config(void) case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_P5600: + case CPU_QEMUR6: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 22b19c275044..b3568c049b72 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c@@ -1486,6 +1486,7 @@ static inline void parity_protection_init(void) case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_P5600: + case CPU_QEMUR6: { #define ERRCTL_PE 0x80000000 #define ERRCTL_L2P 0x00800000
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fbcd8674ff1d..a659770bc539 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c@@ -1243,6 +1243,7 @@ static void probe_pcache(void) case CPU_P5600: case CPU_PROAPTIV: case CPU_M5150: + case CPU_QEMUR6: if (!(read_c0_config7() & MIPS_CONF7_IAR) && (c->icache.waysize > PAGE_SIZE)) c->icache.flags |= MIPS_CACHE_ALIASES;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 99eb8fabab60..6133b2de8a9c 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c@@ -81,6 +81,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) case CPU_PROAPTIV: case CPU_P5600: case CPU_BMIPS5000: + case CPU_QEMUR6: if (config2 & (1 << 12)) return 0; }
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index e3328a96e809..14e5fae71a06 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c@@ -514,6 +514,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_PROAPTIV: case CPU_P5600: case CPU_M5150: + case CPU_QEMUR6: break; default:
--
2.2.0