[PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number
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STALE2803d
SUPERSEDED: 1 (1M)
From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Date: 2019-01-29 08:10:06
Also in:
linux-arm-kernel, linux-pci, lkml
Subsystem:
pci native host bridge and endpoint drivers, pci subsystem, the rest · Maintainers:
Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Linus Torvalds
Revision v3 of 3 in this series; 1 review trailer.
Revisions (3)
- v2 [diff vs current]
- v3 current
- v4 [diff vs current]
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> The reset value is all zero, so set a workable value for Primary, Secondary and Subordinate bus numbers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> --- V3: - No change drivers/pci/controller/pcie-mobiveil.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index db7ecb021c63..9210165fe8c0 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c@@ -582,6 +582,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) u32 value, pab_ctrl, type; struct resource_entry *win; + /* setup bus numbers */ + value = csr_readl(pcie, PCI_PRIMARY_BUS); + value &= 0xff000000; + value |= 0x00ff0100; + csr_writel(pcie, value, PCI_PRIMARY_BUS); + /* * program Bus Master Enable Bit in Command Register in PAB Config * Space
--
2.17.1