Thread (33 messages) 33 messages, 4 authors, 2024-01-17

Re: [PATCH v3 11/12] arm64: dts: exynos: gs101: define USI8 with I2C configuration

From: Tudor Ambarus <tudor.ambarus@linaro.org>
Date: 2024-01-17 15:08:31
Also in: linux-clk, linux-devicetree, linux-i2c, linux-samsung-soc, linux-serial, lkml


On 1/16/24 18:03, Sam Protsenko wrote:
quoted
USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
selection of the protocol is intentionally left for the board dts file.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
v3: reorder usi8 clock order (thanks Andre'!). Did not make any
difference at testing as the usi driver treats the clocks in bulk.
v2:
- identify and use gate clocks instead of dividers
- move cells and pinctrl properties from dts to dtsi
- move IRQ type constant on the previous line

 arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++
 1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 6aa25cc4676e..f14a24628d04 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 {
                        interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
                };

+               usi8: usi@109700c0 {
+                       compatible = "google,gs101-usi",
+                                    "samsung,exynos850-usi";
+                       reg = <0x109700c0 0x20>;
+                       ranges;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>,
+                                <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
+                       clock-names = "pclk", "ipclk";
+                       samsung,sysreg = <&sysreg_peric0 0x101c>;
I'd also add samsung,mode for the "default" USI mode here, just to
avoid providing it later in the board's dts. But that's a matter of
taste I guess.
USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
selection of the protocol is intentionally left for the board dts file.

I wanted to emphasize that USI8 doesn't have any HW defaults and its
mode must be chosen by each particular board.

I mentioned the same in the commit message, please tell if you feel it
needs updating.

Cheers,
ta

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