Hello Chen-Yu,

On Thu, 2022-04-21 at 14:53 +0800, Chen-Yu Tsai wrote:

On Wed, Apr 20, 2022 at 9:05 PM Rex-BC Chen <rex-bc.chen@mediatek.com

quoted

wrote:

The infra_ao reset is needed for MT8192. Therefore, we add this
patch
to support it.

Signed-off-by: Rex-BC Chen <redacted>
---
 drivers/clk/mediatek/clk-mt8192.c         | 11 +++++++++++
 include/dt-bindings/reset/mt8192-resets.h | 11 +++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt8192.c

b/drivers/clk/mediatek/clk-mt8192.c
index ab27cd66b866..7926b83b9035 100644

--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c

@@ -1114,6 +1114,13 @@ static const struct mtk_gate top_clks[] = {
        GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m",

25),
 };

+static const struct mtk_clk_rst_desc clk_rst_desc = {
+       .version = MTK_RST_SET_CLR,
+       .reg_num = 4,
+       .reg_ofs = 0x0,
+       .reset_n_cells = 2,

If you want to do this, you need to update the bindings first.

OK, I will add another patch for this.

quoted

+};
+
 #define MT8192_PLL_FMAX                (3800UL * MHZ)
 #define MT8192_PLL_FMIN                (1500UL * MHZ)
 #define MT8192_INTEGER_BITS    8

@@ -1239,6 +1246,10 @@ static int clk_mt8192_infra_probe(struct

platform_device *pdev)
        if (r)
                goto free_clk_data;

+       r = mtk_clk_register_rst_ctrl_with_dev(&pdev->dev,
&clk_rst_desc);
+       if (r)
+               goto free_clk_data;
+
        r = of_clk_add_provider(node, of_clk_src_onecell_get,
clk_data);
        if (r)
                goto free_clk_data;

diff --git a/include/dt-bindings/reset/mt8192-resets.h

b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..feac1ac85906 100644

--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h

@@ -7,6 +7,7 @@
 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192

+/* TOPRGU */
 #define

MT8192_TOPRGU_MM_SW_RST                                        1
 #define MT8192_TOPRGU_MFG_SW_RST                               2
 #define MT8192_TOPRGU_VENC_SW_RST                              3

@@ -27,4 +28,14 @@

 #define MT8192_TOPRGU_SW_RST_NUM                               23

+/* INFRA RST0 */
+#define MT8192_INFRA_RST0_LVTS_AP_RST                          0
+/* INFRA RST2 */
+#define MT8192_INFRA_RST2_PCIE_PHY_RST                         15
+/* INFRA RST3 */
+#define MT8192_INFRA_RST3_PTP_RST                              5
+/* INFRA RST4 */
+#define MT8192_INFRA_RST4_LVTS_MCU                             12
+#define MT8192_INFRA_RST4_PCIE_TOP                             1
+

This change should be part of the binding change.

For these, please also add a patch for the actual device tree
changes.

OK, I will do this.

BRs,
Rex

ChenYu

quoted

 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
--
2.18.0

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