Re: [PATCH RESEND 0/3] Represent cluster topology and enable load balance between clusters
From: Barry Song <hidden>
Date: 2021-10-05 09:06:48
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On Tue, Oct 5, 2021 at 9:05 PM Peter Zijlstra [off-list ref] wrote:
On Sat, Oct 02, 2021 at 08:09:58PM +1300, Barry Song wrote:quoted
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 7e4651a1aaf4..86821e83b935 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig@@ -993,8 +993,13 @@ config SCHED_CLUSTER bool "Cluster scheduler support" help Cluster scheduler support improves the CPU scheduler's decision + making when dealing with machines that have clusters of CPUs. + Cluster usually means a couple of CPUs which are placed closely + by sharing mid-level caches, last-level cache tags or internal + busses. For example, on Hisilicon Kunpeng920, each 4 CPUs share + LLC cache tags. This feature isn't a universal win because it + can bring a cost of slightly increased overhead in some places. + If unsure say N here. config SCHED_SMT bool "SMT scheduler support"diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index bd27b1cdac34..940eb1fe0abb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig@@ -1002,12 +1002,17 @@ config NR_CPUS to the kernel image. config SCHED_CLUSTER + def_bool y + prompt "Cluster scheduler support" help Cluster scheduler support improves the CPU scheduler's decision + making when dealing with machines that have clusters of CPUs. + Cluster usually means a couple of CPUs which are placed closely + by sharing mid-level caches, last-level cache tags or internal + busses. For example, on x86 Jacobsville, each 4 CPUs share one + L2 cache.This feature isn't a universal win because it can bringquoted
+ a cost of slightly increased overhead in some places. If unsure + say N here.That is a really odd addition to a default-y feature. How about I make both: help Cluster scheduler support improves the CPU scheduler's decision making when dealing with machines that have clusters of CPUs. Cluster usually means a couple of CPUs which are placed closely by sharing mid-level caches, last-level cache tags or internal busses.
looks good to me. thanks! barry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel