Hi Andrew,

Thanks a lot for your comments!

-----Original Message-----
From: Andrew Murray <redacted>
Sent: 2020年1月13日 19:32
To: Z.q. Hou <zhiqiang.hou@nxp.com>
Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
bhelgaas@google.com; robh+dt@kernel.org; arnd@arndb.de;
mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
shawnguo@kernel.org; m.karthikeyan@mobiveil.co.in; Leo Li
[off-list ref]; lorenzo.pieralisi@arm.com;
catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
[off-list ref]; M.h. Lian [off-list ref]; Xiaowei Bao
[off-list ref]
Subject: Re: [PATCHv9 08/12] PCI: mobiveil: Add 8-bit and 16-bit CSR register
accessors

On Wed, Nov 20, 2019 at 03:46:10AM +0000, Z.q. Hou wrote:

quoted

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

There are some 8-bit and 16-bit registers in PCIe configuration space,
so add these accessors accordingly.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <redacted>
---
V9:
 - No change

 .../pci/controller/mobiveil/pcie-mobiveil.h   | 23

+++++++++++++++++++

quoted

 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h

b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 37116c2a19fe..750a7fd95bc1 100644

--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h

@@ -182,10 +182,33 @@ static inline u32 mobiveil_csr_readl(struct

mobiveil_pcie *pcie, u32 off)

quoted

 	return mobiveil_csr_read(pcie, off, 0x4);  }

+static inline u32 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32
+off) {
+	return mobiveil_csr_read(pcie, off, 0x2); }
+
+static inline u32 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32
+off) {
+	return mobiveil_csr_read(pcie, off, 0x1); }

Do you think the above two return types should reflect the size of the access?

Will change in v10.

Thanks,
Zhiqiang

Thanks,

Andrew Murray

quoted

+
+
 static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val,
 				       u32 off)
 {
 	mobiveil_csr_write(pcie, val, off, 0x4);  }

+static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u32 val,
+				       u32 off)
+{
+	mobiveil_csr_write(pcie, val, off, 0x2); }
+
+static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u32 val,
+				       u32 off)
+{
+	mobiveil_csr_write(pcie, val, off, 0x1); }
+
 #endif /* _PCIE_MOBIVEIL_H */
--
2.17.1

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