Re: [PATCHv9 08/12] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
From: Andrew Murray <hidden>
Date: 2020-01-13 11:31:39
Also in:
linux-devicetree, linux-pci, lkml
On Wed, Nov 20, 2019 at 03:46:10AM +0000, Z.q. Hou wrote:
quoted hunk ↗ jump to hunk
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> There are some 8-bit and 16-bit registers in PCIe configuration space, so add these accessors accordingly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <redacted> --- V9: - No change .../pci/controller/mobiveil/pcie-mobiveil.h | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+)diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 37116c2a19fe..750a7fd95bc1 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h@@ -182,10 +182,33 @@ static inline u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off) return mobiveil_csr_read(pcie, off, 0x4); } +static inline u32 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32 off) +{ + return mobiveil_csr_read(pcie, off, 0x2); +} + +static inline u32 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32 off) +{ + return mobiveil_csr_read(pcie, off, 0x1); +}
Do you think the above two return types should reflect the size of the access? Thanks, Andrew Murray
+
+
static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val,
u32 off)
{
mobiveil_csr_write(pcie, val, off, 0x4);
}
+static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u32 val,
+ u32 off)
+{
+ mobiveil_csr_write(pcie, val, off, 0x2);
+}
+
+static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u32 val,
+ u32 off)
+{
+ mobiveil_csr_write(pcie, val, off, 0x1);
+}
+
#endif /* _PCIE_MOBIVEIL_H */
--
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