On 2018-01-29 10:41, Sricharan R wrote:

  s/IPQ40xx/IPQ4019

+
+	soc {
+		pcie0: pci at 40000000 {
+			status = "disabled";
+		};

  We can disable in base dtsi itself.

+
+		pinctrl at 1000000 {
+			serial_1_pins: serial1_pinmux {
+				mux {
+					pins = "gpio8", "gpio9";
+					function = "blsp_uart1";
+					bias-disable;
+				};
+			};
+
+			spi_0_pins: spi_0_pinmux {
+				mux {
+					pins = "gpio13", "gpio14",
"gpio15";
+					function = "blsp_spi0";
+					bias-disable;
+				};
+				cs1 {
+					pins = "gpio12";
+					function = "gpio";
+				};
+				host_int1 {
+					pins = "gpio10";
+					function = "gpio";
+					input;
+				};
+				cs2 {
+					pins = "gpio45";
+					function = "gpio";
+				};
+				host_int2 {
+					pins = "gpio61";
+					function = "gpio";
+					input;
+				};
+				rst {
+					pins = "gpio36";
+					function = "gpio";
+					output-high;
+				};

  Normally spi pins should contains spi protocol related pins
  could you please explain what is the role of host_pin and rst
  pins and which driver will use these.

+			};
+		};
+
+		serial at 78b0000 {
+			pinctrl-0 = <&serial_1_pins>;
+			pinctrl-names = "default";
+			status = "ok";
+		};
+
+		spi_0: spi at 78b5000 { /* BLSP1 QUP1 */
+			pinctrl-0 = <&spi_0_pins>;
+			pinctrl-names = "default";
+			status = "ok";

  From pinmux, it looks like multiple gpio based cs are being
  used so do we need to specify cs-gpios like dk01-c2.

  Thanks,
  Abhishek

+
+			spidev0_0 {
+				compatible = "spidev";
+				reg = <0>;
+				spi-max-frequency = <24000000>;
+			};
+			spidev0_1 {
+				compatible = "spidev";
+				reg = <1>;
+				spi-max-frequency = <24000000>;
+			};
+		};
+	};
+};