[PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
From: Chen-Yu Tsai <hidden>
Date: 2014-05-23 08:27:41
Also in:
linux-devicetree, linux-serial, lkml
Subsystem:
arm/allwinner soc clock support, common clk framework, the rest · Maintainers:
Emilio López, Michael Turquette, Stephen Boyd, Linus Torvalds