[PATCH 06/12] pcie: designware: Move register definition to the header file
From: Mohit KUMAR DCG <hidden>
Date: 2013-12-11 11:55:42
Also in:
linux-pci
Hello Jagan,
-----Original Message----- From: Jagan Teki [mailto:jagannadh.teki at gmail.com] Sent: Wednesday, December 11, 2013 5:09 PM To: Mohit KUMAR DCG Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Pratyush ANAND; Jingoo Han; spear-devel Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the header file On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar [off-list ref] wrote:quoted
From: Pratyush Anand <redacted> Move synopsis specific register definition from source file to header file, so that they can be re-used by other files if needed. Signed-off-by: Pratyush Anand <redacted> Cc: Mohit Kumar <redacted> Cc: Jingoo Han <redacted> Cc: spear-devel at list.st.com Cc: linux-pci at vger.kernel.org --- drivers/pci/host/pcie-designware.c | 42 ------------------------------------ drivers/pci/host/pcie-designware.h | 42++++++++++++++++++++++++++++++++++++quoted
2 files changed, 42 insertions(+), 42 deletions(-)diff --git a/drivers/pci/host/pcie-designware.cb/drivers/pci/host/pcie-designware.c index 212b8b6..73aa13c 100644--- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c@@ -23,48 +23,6 @@ #include "pcie-designware.h" -/* Synopsis specific PCIE configuration registers */ -#define PCIE_PORT_LINK_CONTROL 0x710 -#define PORT_LINK_MODE_MASK (0x3f << 16) -#define PORT_LINK_MODE_1_LANES (0x1 << 16) -#define PORT_LINK_MODE_2_LANES (0x3 << 16) -#define PORT_LINK_MODE_4_LANES (0x7 << 16) - -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C -#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) -#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) -#definePORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) -#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) - -#define PCIE_MSI_ADDR_LO 0x820 -#define PCIE_MSI_ADDR_HI 0x824 -#define PCIE_MSI_INTR0_ENABLE 0x828 -#define PCIE_MSI_INTR0_MASK 0x82C -#define PCIE_MSI_INTR0_STATUS 0x830 - -#define PCIE_ATU_VIEWPORT 0x900 -#define PCIE_ATU_REGION_INBOUND (0x1 << 31) -#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) -#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) -#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) -#define PCIE_ATU_CR1 0x904 -#define PCIE_ATU_TYPE_MEM (0x0 << 0) -#define PCIE_ATU_TYPE_IO (0x2 << 0) -#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) -#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) -#define PCIE_ATU_CR2 0x908 -#define PCIE_ATU_ENABLE (0x1 << 31) -#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) -#define PCIE_ATU_LOWER_BASE 0x90C -#define PCIE_ATU_UPPER_BASE 0x910 -#define PCIE_ATU_LIMIT 0x914 -#define PCIE_ATU_LOWER_TARGET 0x918 -#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) -#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) -#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) -#define PCIE_ATU_UPPER_TARGET 0x91C - static struct hw_pci dw_pci; static unsigned long global_io_offset; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index c15379b..da1ed35 100644--- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h@@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp); voiddw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +/* Synopsis specific PCIE configuration registers */ +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_MODE_MASK (0x3f << 16) +#define PORT_LINK_MODE_1_LANES (0x1 << 16) +#define PORT_LINK_MODE_2_LANES (0x3 << 16) +#define PORT_LINK_MODE_4_LANES (0x7 << 16) + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) +#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) #define +PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) #define +PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) + +#define PCIE_MSI_ADDR_LO 0x820 +#define PCIE_MSI_ADDR_HI 0x824 +#define PCIE_MSI_INTR0_ENABLE 0x828 +#define PCIE_MSI_INTR0_MASK 0x82C +#define PCIE_MSI_INTR0_STATUS 0x830 + +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + #endif /* _PCIE_DESIGNWARE_H */Seems like none were using these headers except pcie-designware.c - if ie the case better to place it same place as before.
- We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL ' for SPEAr13xx platform, so move these to the separate header file. Thanks Mohit
-- Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki at gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki